Invention Grant
- Patent Title: Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same
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Application No.: US15151503Application Date: 2016-05-11
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Publication No.: US09881924B2Publication Date: 2018-01-30
- Inventor: Kuo-Chen Wang , Shih-Fan Kuan , Lars Heineck , Sanh Tang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G11C5/06
- IPC: G11C5/06 ; H01L27/108 ; H01L21/8242 ; H01L29/06 ; H01L23/528 ; H01L23/522 ; H01L23/532 ; H01L21/027 ; H01L21/311 ; H01L21/3105 ; H01L21/762

Abstract:
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
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