公开(公告)号：US10679958B2

公开(公告)日：2020-06-09

申请号：US16195241

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/538 ,  H01L21/82 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/525

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US20200294945A1

公开(公告)日：2020-09-17

申请号：US16890546

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/82 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US10593637B2

公开(公告)日：2020-03-17

申请号：US16108473

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/538 ,  H01L21/82 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/525

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US20190088606A1

公开(公告)日：2019-03-21

申请号：US16195241

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H01L21/82 ,  H01L23/538 ,  H01L23/525 ,  H01L23/498

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US20180358315A1

公开(公告)日：2018-12-13

申请号：US16108473

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/525 ,  H01L23/498

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US20170330882A1

公开(公告)日：2017-11-16

申请号：US15151503

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US11211351B2

公开(公告)日：2021-12-28

申请号：US16890546

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Shih-Fan Kuan ,  Yi-Jen Lo

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/538 ,  H01L21/82 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/525

Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

公开(公告)号：US10566332B2

公开(公告)日：2020-02-18

申请号：US16192097

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US10381302B2

公开(公告)日：2019-08-13

申请号：US15396817

申请日：2017-01-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Shih-Fan Kuan ,  Tieh-Chiang Wu

IPC: H01L21/48 ,  H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065

Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.

公开(公告)号：US10163909B2

公开(公告)日：2018-12-25

申请号：US15840972

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L21/027 ,  H01L21/762 ,  H01L23/528 ,  H01L27/108 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.