公开(公告)号：US09881924B2

公开(公告)日：2018-01-30

申请号：US15151503

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/8242 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US10163909B2

公开(公告)日：2018-12-25

申请号：US15840972

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L21/027 ,  H01L21/762 ,  H01L23/528 ,  H01L27/108 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US20180102366A1

公开(公告)日：2018-04-12

申请号：US15840972

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/532 ,  H01L21/027 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

公开(公告)号：US20170330882A1

公开(公告)日：2017-11-16

申请号：US15151503

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh Tang

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L27/10823 ,  H01L21/0273 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/0649

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.