Invention Grant
- Patent Title: Method for forming a semiconductor device and a semiconductor device
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Application No.: US15413579Application Date: 2017-01-24
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Publication No.: US09911808B2Publication Date: 2018-03-06
- Inventor: Hans-Joachim Schulze , Philipp Seng
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater Matsil, LLP
- Priority: DE102016102070 20160205
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/425 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119 ; H01L29/06 ; H01L21/265 ; H01L21/326 ; H01L29/10 ; H01L29/167 ; H01L29/36 ; H01L29/66 ; H01L29/739 ; H01L29/78 ; H01L29/861

Abstract:
A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.
Public/Granted literature
- US20170229539A1 Method for Forming a Semiconductor Device and a Semiconductor Device Public/Granted day:2017-08-10
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