公开(公告)号：US10516065B2

公开(公告)日：2019-12-24

申请号：US15642893

申请日：2017-07-06

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Dieter Pfirsch ,  Hans-Joachim Schulze ,  Philipp Seng ,  Armin Willmeroth

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/861 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/36 ,  H01L21/225 ,  H01L21/266 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265

Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

公开(公告)号：US20250107115A1

公开(公告)日：2025-03-27

申请号：US18826506

申请日：2024-09-06

Applicant: Infineon Technologies AG

Inventor： Manfred Pfaffenlehner ,  Arnab Biswas ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Philipp Seng

IPC: H01L29/861 ,  H01L27/06

Abstract: A power semiconductor diode includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body coupled to an anode region of a second conductivity type in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body coupled to both cathode regions of the first conductivity type and short regions of the second conductivity type of a doped region in the semiconductor body and coupled to the drift region; and a resistive element external of the semiconductor body. The diode conducts a load current between the load terminals, a first path of which crosses the anode region, drift region and cathode regions and a second path of which crosses the anode region, drift region and short regions. The resistive element exhibits a resistance having a positive-temperature-coefficient.

公开(公告)号：US09911808B2

公开(公告)日：2018-03-06

申请号：US15413579

申请日：2017-01-24

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Philipp Seng

IPC: H01L21/00 ,  H01L21/425 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L21/265 ,  H01L21/326 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/0684 ,  H01L21/26513 ,  H01L21/326 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66666 ,  H01L29/7395 ,  H01L29/7827 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.

公开(公告)号：US20180013013A1

公开(公告)日：2018-01-11

申请号：US15642893

申请日：2017-07-06

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Dieter Pfirsch ,  Hans-Joachim Schulze ,  Philipp Seng ,  Armin Willmeroth

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/225 ,  H01L21/266

CPC classification number: H01L29/8611 ,  H01L21/2253 ,  H01L21/2652 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0688 ,  H01L29/08 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66136

Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

公开(公告)号：US20170229539A1

公开(公告)日：2017-08-10

申请号：US15413579

申请日：2017-01-24

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Philipp Seng

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/739 ,  H01L21/326 ,  H01L29/78 ,  H01L29/861 ,  H01L29/10 ,  H01L29/36 ,  H01L29/167

CPC classification number: H01L29/0684 ,  H01L21/26513 ,  H01L21/326 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66666 ,  H01L29/7395 ,  H01L29/7827 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes incorporating first dopant atoms of a first conductivity type into a semiconductor substrate to form a first doping region of the first conductivity type. Further, the method includes forming an epitaxial semiconductor layer on the semiconductor substrate and incorporating second dopant atoms of a second conductivity type before or after forming the epitaxial semiconductor layer to form a second doping region including the second conductivity type adjacent to the first doping region so that a pn-junction is located between the first doping region and the second doping region. The pn-junction is located in a vertical distance of less than 5 μm to an interface between the semiconductor substrate and the epitaxial semiconductor layer. Additionally, the method includes thinning the semiconductor substrate based on a self-aligned thinning process. The self-aligned thinning process is self-controlled based on the location of the pn-junction.