Invention Grant
- Patent Title: Extra doped region for back-side deep trench isolation
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Application No.: US14923635Application Date: 2015-10-27
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Publication No.: US09954022B2Publication Date: 2018-04-24
- Inventor: Chun-Yuan Chen , Ching-Chun Wang , Dun-Nian Yaung , Hsiao-Hui Tseng , Jhy-Jyi Sze , Shyh-Fann Ting , Tzu-Jui Wang , Yen-Ting Chiang , Yu-Jen Wang , Yuichiro Yamashita
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L31/00
- IPC: H01L31/00 ; H01L27/146

Abstract:
The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.
Public/Granted literature
- US20170117309A1 EXTRA DOPED REGION FOR BACK-SIDE DEEP TRENCH ISOLATION Public/Granted day:2017-04-27
Information query
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