公开(公告)号：US11984353B2

公开(公告)日：2024-05-14

申请号：US17352812

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Han Tseng ,  Chun-Yuan Chen ,  Lu-Sheng Chou ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze

IPC: H01L21/768 ,  H01L49/02

CPC classification number: H01L21/76832 ,  H01L21/76831 ,  H01L28/88

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US20220130888A1

公开(公告)日：2022-04-28

申请号：US17646765

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Chih-Yu Lai ,  Shih Pei Chou ,  Yen-Ting Chiang ,  Hsiao-Hui Tseng ,  Min-Ying Tsai

IPC: H01L27/146 ,  H01L29/06 ,  H01L21/762

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

公开(公告)号：US20170133414A1

公开(公告)日：2017-05-11

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US20170117309A1

公开(公告)日：2017-04-27

申请号：US14923635

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

公开(公告)号：US10777590B2

公开(公告)日：2020-09-15

申请号：US16591136

申请日：2019-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Chun-Yuan Chen ,  Hsiao-Hui Tseng ,  Yu-Jen Wang ,  Shyh-Fann Ting ,  Wei-Chuang Wu ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/11

Abstract: A method for forming an image sensor device structure is provided. The method includes forming a light-sensing region in a substrate, and forming an interconnect structure below a first surface of the substrate. The method also includes forming a trench in the light-sensing region from a second surface of the substrate, and forming a doping layer in the trench. The method includes forming an oxide layer in the trench and on the doping layer to form a doping region, and the doping region is inserted into the light-sensing region.

公开(公告)号：US20200066770A1

公开(公告)日：2020-02-27

申请号：US16674216

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.

公开(公告)号：US10276618B2

公开(公告)日：2019-04-30

申请号：US15919784

申请日：2018-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L31/00 ,  H01L27/146

Abstract: The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

公开(公告)号：US09954022B2

公开(公告)日：2018-04-24

申请号：US14923635

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L31/00 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

公开(公告)号：US20170301709A1

公开(公告)日：2017-10-19

申请号：US15635673

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

公开(公告)号：US09536810B1

公开(公告)日：2017-01-03

申请号：US14737979

申请日：2015-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Hsiao-Hui Tseng ,  Ming-Tsong Wang ,  Shyh-Fann Ting ,  Wei Chuang Wu

IPC: H01L23/482 ,  H01L27/146 ,  H01L23/485 ,  H01L23/48 ,  H01L23/528 ,  H01L31/05 ,  H01L31/0224

CPC classification number: H01L23/4824 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L31/0224 ,  H01L31/05 ,  H01L31/0508

Abstract: A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line (BEOL) metallization stack, and comprises a scribe line opening. A buffer layer lines the scribe line opening. A conductive pad comprises a base region and a protruding region. The base region is arranged over the buffer layer in the scribe line opening, and the protruding region protrudes from the base region into the BEOL metallization stack. A dielectric layer fills the scribe line opening over the conductive pad, and is substantially flush with an upper surface of the semiconductor substrate. Further, a method for manufacturing the pad structure, as well as the CMOS image sensor, are provided.

Abstract translation: 提供了一种用于互补金属氧化物半导体（CMOS）图像传感器的焊盘结构。 半导体衬底布置在线的后端（BEOL）金属化叠层上，并且包括划线开口。 缓冲层划线划线开口。 导电焊盘包括基极区域和突出区域。 基部区域布置在划线开口中的缓冲层上方，并且突出区域从基部区域突出到BEOL金属化堆叠中。 电介质层填充导电焊盘上的划线，并且与半导体衬底的上表面基本齐平。 此外，提供了一种用于制造焊盘结构的方法以及CMOS图像传感器。