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    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM
    1.
    发明授权
    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM 有权
    可扩展性，KOMPONENTENANWÄHLBARE和高网络三个组成部分安排在一个系统

    公开(公告)号：EP1787184B1

    公开(公告)日：2011-05-04

    申请号：EP05792874.9

    申请日：2005-08-30

    申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    发明人： KUEKES, Phillip, J. ,  WILLIAMS, R., Stanley, ,  BEAUSOLEIL, Raymond, G.

    IPC分类号： G06F1/18 ,  H05K7/14

    CPC分类号： G06F1/18 ,  G06F17/509 ,  H05K7/1444

    摘要： Embodiments of the present invention include dense, but assessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a 'flat components' (202, 206), are arranged into local blocks (400) of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-block repeating units (700), and the primitive local-block repeating units are layered togehter in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume (Figure 9). The arrangement provides for relatively short, direct pathways (1312-1320) from the surface of the specificed volume to any particular local block component within the three-dimensional arrangement.

    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS
    4.
    发明公开
    ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS 审中-公开
    在集成电路活性化合物和控制点

    公开(公告)号：EP1872398A2

    公开(公告)日：2008-01-02

    申请号：EP06750806.9

    申请日：2006-04-19

    申请人： Hewlett-Packard Development Company, L.P.

    发明人： WILLIAMS, R., Stanley ,  KUEKES, Phillip, J. ,  PERNER, Frederick, A. ,  SNIDER, Gregory, S. ,  STEWART, Duncan

    IPC分类号： H01L21/66

    CPC分类号： H05K7/1092 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.

    THREE-DIMENSIONAL NANOSCALE CROSSBARS
    5.
    发明授权
    THREE-DIMENSIONAL NANOSCALE CROSSBARS 有权
    三根横梁纳米区

    公开(公告)号：EP1875476B1

    公开(公告)日：2011-07-27

    申请号：EP06751576.7

    申请日：2006-04-25

    申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    发明人： WILLIAMS, R., Stanley ,  KUEKES, Phillip, J.

    IPC分类号： G11C13/02

    CPC分类号： H04L49/40 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  H04L49/101 ,  Y10S977/762 ,  Y10S977/767

    摘要： Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed (1016) in three independent directions, and in which electronic components can be fabricated at junctions (510, 802) interconnected by internal signal lines ( 502-509 and 702-709). The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.

    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM
    7.
    发明公开
    SCALABLE, COMPONENT-ACCESSIBLE, AND HIGHLY INTERCONNECTED THREE-DIMENSIONAL COMPONENT ARRANGEMENT WITHIN A SYSTEM 有权
    可扩展性，KOMPONENTENANWÄHLBARE和高网络三个组成部分安排在一个系统

    公开(公告)号：EP1787184A1

    公开(公告)日：2007-05-23

    申请号：EP05792874.9

    申请日：2005-08-30

    申请人： Hewlett-Packard Development Company, L.P.

    发明人： KUEKES, Phillip, J. ,  WILLIAMS, R., Stanley, ,  BEAUSOLEIL, Raymond, G.

    IPC分类号： G06F1/18 ,  H05K7/14

    CPC分类号： G06F1/18 ,  G06F17/509 ,  H05K7/1444

    摘要： Embodiments of the present invention include dense, but assessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a 'flat components' (202, 206), are arranged into local blocks (400) of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-block repeating units (700), and the primitive local-block repeating units are layered togehter in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume (Figure 9). The arrangement provides for relatively short, direct pathways (1312-1320) from the surface of the specificed volume to any particular local block component within the three-dimensional arrangement.

    THREE-DIMENSIONAL NANOSCALE CROSSBARS
    8.
    发明公开
    THREE-DIMENSIONAL NANOSCALE CROSSBARS 有权
    三根横梁纳米区

    公开(公告)号：EP1875476A1

    公开(公告)日：2008-01-09

    申请号：EP06751576.7

    申请日：2006-04-25

    申请人： Hewlett-Packard Development Company, L.P.

    发明人： WILLIAMS, R., Stanley ,  KUEKES, Phillip, J.

    IPC分类号： G11C13/02

    CPC分类号： H04L49/40 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  H04L49/101 ,  Y10S977/762 ,  Y10S977/767

    摘要： Various embodiments of the present invention include three-dimensional, at least partially nanoscale, electronic circuits and devices in which signals can be routed (1016) in three independent directions, and in which electronic components can be fabricated at junctions (510, 802) interconnected by internal signal lines ( 502-509 and 702-709). The three-dimensional, at least partially nanoscale, electronic circuits and devices include layers, the nanowire or microscale-or-submicroscale/nanowire junctions of each of which may be economically and efficiently fabricated as one type of electronic component. Various embodiments of the present invention include nanoscale memories, nanoscale programmable arrays, nanoscale multiplexers and demultiplexers, and an almost limitless number of specialized nanoscale circuits and nanoscale electronic components.

    NANOSCALE INTERCONNECTION INTERFACE
    9.
    发明公开
    NANOSCALE INTERCONNECTION INTERFACE 有权
    VERBINDUNGSSCHNITTSTELLE IM NANOBEREICH

    公开(公告)号：EP1875352A2

    公开(公告)日：2008-01-09

    申请号：EP06758634.7

    申请日：2006-04-26

    申请人： Hewlett-Packard Development Company, L.P.

    发明人： KUEKES, Phillip, J. ,  ROBINETT, Warren, J. ,  SEROUSSI, Gadiel ,  WILLIAMS, R., Stanley

    IPC分类号： G06F11/10

    CPC分类号： G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

    摘要： One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2k nanowire addresses to a larger, internal, n-bit address space, where n > k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n > k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    摘要翻译： 本发明的一个实施例提供了实现为纳米线交叉开关的解复用器或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，使用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，良好分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。