CONTEXT IDENTIFICATION USING A DENOISED SIGNAL
    6.
    发明公开
    CONTEXT IDENTIFICATION USING A DENOISED SIGNAL 审中-公开
    上下文识别使用信号降噪

    公开(公告)号:EP1902422A1

    公开(公告)日:2008-03-26

    申请号:EP05824448.4

    申请日:2005-10-31

    IPC分类号: G06T5/00

    摘要: Denoising such as discrete universal denoising (DUDE) that scans a noisy signal in an attempt to characterize probabilities of finding symbol values in a particular context in a clean signal can perform a rough denoising (1230) on the noisy signal and identify contexts from a roughly denoised signal. The rough denoising (1230) improves estimation of the statistical properties of the clean signal by reducing the false differentiation of contects that noise can otherwise create. Statistical information regarding occurrences of symbols in the noisy signal and corresponding contexts in the roughly denoised signal can then be used to denoise the noisy signal. The specifics of the rough denoising (1230) can be chosen based on knowledge of the noise or of clean date Alternatively, the DUDE can be used in an iterative fashion where the denoised signal produced from a prior iteration provides the contexts for the next iteration.

    NANOSCALE INTERCONNECTION INTERFACE
    7.
    发明公开
    NANOSCALE INTERCONNECTION INTERFACE 有权
    VERBINDUNGSSCHNITTSTELLE IM NANOBEREICH

    公开(公告)号:EP1875352A2

    公开(公告)日:2008-01-09

    申请号:EP06758634.7

    申请日:2006-04-26

    IPC分类号: G06F11/10

    摘要: One embodiment of the present invention provides a demultiplexer implemented as a nonowire crossbar (3000) or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines (3003, 3004) to 2k or fewer nanowires (3006-3009), employing supplemental, internal address lines (3010, 3012) to map 2k nanowire addresses to a larger, internal, n-bit address space, where n > k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n > k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire address to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    摘要翻译: 本发明的一个实施例提供了实现为纳米线交叉开关的解复用器或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用,使用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间,其中n> k。 本发明的第二解复用器实施例使用2k,良好分布的n位外部地址来访问2k纳米线,在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法,或者评估纳米线与不同大小的外部地址空间的映射,用于评估地址映射和解复用器设计的度量,以及 解复用器设计方法。

    DISCRETE UNIVERSAL DENOISING WITH RELIABILITY INFORMATION
    8.
    发明公开
    DISCRETE UNIVERSAL DENOISING WITH RELIABILITY INFORMATION 审中-公开
    DISCREET UNIVERS埃尔斯与ZUVERLÄSSIGKEITSINFORMATIONEN减噪

    公开(公告)号:EP1766911A1

    公开(公告)日:2007-03-28

    申请号:EP05763641.7

    申请日:2005-06-24

    IPC分类号: H04L25/06 H04L1/00

    CPC分类号: H04L1/0045 H04L25/067

    摘要: A method of and system for generating reliability information (1616) for a noisy signal (1612) received through a noise-introducing channel (1606). In one embodiment, symbol-transition probabilities are determined for the noise-introducing channel (1606). Occurrences of metasymbols in the noisy signal (1612) are counted, each metasymbol providing a context for a symbol of the metasymbol. For each metasymbol occuring in the noisy signal, reliability information (1616) for each possible value of the symbol of the metasymbol is determined, the reliability information (1616) representing a proability that the value in the original signal corresponding to the symbol of the metasymbol assumed each of the possible values. In another embodiment, error correction coding may be performed by adding redundant data to an original signal prior (1600) to transmission by the noise-introducing channel (1606) and performing error correction decoding after transmission.

    METHOD AND SYSTEM FOR COMPRESSING BITPLANES BASED ON BIT POSITION
    9.
    发明公开
    METHOD AND SYSTEM FOR COMPRESSING BITPLANES BASED ON BIT POSITION 审中-公开
    基于比特位置的方法和系统进行压缩过的位平面

    公开(公告)号:EP2599351A1

    公开(公告)日:2013-06-05

    申请号:EP10855423.9

    申请日:2010-07-26

    IPC分类号: H04W52/02 H04W28/06 H04L12/28

    摘要: A technology is provided for compressing digital discrete node data to reduce overall power consumption. Node data can be represented by a plurality of data units with a specified data width and can also be viewed as a plurality of bit planes corresponding to data at each bit position for the data units. A threshold bit position value may be selected for data units using an achievable compressibility estimate relative to an estimated energy consumption. The threshold bit position value can represent a boundary where an estimated energy consumption for compressing and transmitting a bit plane is less than an estimated energy consumption for transmitting the bit plane uncompressed. A bit plane is selected in the plurality of bit planes with a bit position value greater than the threshold bit position value. The bit plane is compressed using a compressor in the networked node.

    DEFECT-TOLERANT AND FAULT-TOLERANT CIRCUIT INTERCONNECTIONS
    10.
    发明公开
    DEFECT-TOLERANT AND FAULT-TOLERANT CIRCUIT INTERCONNECTIONS 审中-公开
    FAULT宽容和容错电路连接

    公开(公告)号:EP1665276A2

    公开(公告)日:2006-06-07

    申请号:EP04783547.5

    申请日:2004-09-08

    IPC分类号: G11C8/20 G06F11/10

    摘要: Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described. In the described embodiment, in order to interconnect microelectronic address lines with the nanowire crossbars within the electronic memory, an address encoding technique is employed to generate a number of redundant, parity-check address lines to supplement a minimally required set of address signal lines needed to access the nanoscale memory elements.