公开(公告)号：EP4239666A1

公开(公告)日：2023-09-06

申请号：EP23154863.7

申请日：2023-02-03

申请人： INTEL Corporation

发明人： GULER, Leonard ,  BEASLEY, Madeleine ,  GARDINER, Allen ,  SHIRAZI, Aryan ,  GHANI, Tahir ,  SUBRAMANIAN, Sairam

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices (102b, 102c) each include a semiconductor region (110) extending between a source region and a drain region, and a gate structure (112) extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure (114) that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

公开(公告)号：EP4148776A1

公开(公告)日：2023-03-15

申请号：EP22189218.5

申请日：2022-08-08

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  GHANI, Tahir ,  PATEL, Pratik ,  GULER, Leonard ,  ONG, Clifford ,  HARAN, Mohit

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06

摘要： Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device (102) may be a GAA transistor with a first number of semiconductor nanoribbons (112a) while the n-channel device (104) may be a GAA transistor with a second number of semiconductor nanoribbons (112b) that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

公开(公告)号：EP4109556A1

公开(公告)日：2022-12-28

申请号：EP22163378.7

申请日：2022-03-21

申请人： Intel Corporation

发明人： GHANI, Tahir ,  GOLONZKA, Oleg ,  WALLACE, Charles ,  GULER, Leonard

IPC分类号： H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/08

摘要： Released fins (108), preferably comprising nanowires (112), for advanced integrated circuit structure fabrication, such as nanowire FETs and finFETs are described. An integrated circuit structure includes a substrate (102), a sub-fin (104), a dielectric spacer material (124) on the sub-fin and a fin (108) on the dielectric spacer material. A void (126) is present in the dielectric spacer material, vertically and laterally between the sub-fin and the fin.

公开(公告)号：EP4109511A1

公开(公告)日：2022-12-28

申请号：EP22169682.6

申请日：2022-04-25

申请人： INTEL Corporation

发明人： GULER, Leonard ,  YEMENICIOGLU, Sukru ,  KOLLURU, Kalyan C. ,  KOBRINSKY, Mauro J. ,  WALLACE, Charles H. ,  GHANI, Tahir

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/775

摘要： Integrated circuit structures having backside self-aligned conductive pass-through contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive pass-through contacts, are described. An integrated circuit structure includes a first sub-fin structure (104) over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A dummy gate electrode (112A) is laterally between the first stack of nanowires and the second stack of nanowires. A conductive pass-through contact (130) is laterally between the first stack of nanowires and the second stack of nanowires. The conductive pass-through contact is on and in contact with the dummy gate electrode.

公开(公告)号：EP4203642A1

公开(公告)日：2023-06-28

申请号：EP22208799.1

申请日：2022-11-22

申请人： INTEL Corporation

发明人： ONG, Clifford ,  GULER, Leonard ,  HASAN, Mohammad ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors (130) having a different number of active channel regions than the number of active channel regions in pull-down transistors (125). A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions (605) are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

公开(公告)号：EP4203641A1

公开(公告)日：2023-06-28

申请号：EP22205746.5

申请日：2022-11-07

申请人： INTEL Corporation

发明人： ONG, Clifford ,  LAVRIC, Dan ,  GULER, Leonard ,  CHIU Yen Ting ,  SHRIDHARAN, Smita ,  GUO, Zheng ,  KARL, Eric A. ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors (292) and pull-down transistors (291) having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：EP4105979A1

公开(公告)日：2022-12-21

申请号：EP22166383.4

申请日：2022-04-01

申请人： INTEL Corporation

发明人： GHANI, Tahir ,  WALLACE, Charles ,  GULER, Leonard

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a backside removal approach, are described. For example, an integrated circuit structure includes a first insulator sub-fin structure over a first stack of nanowires. A second insulator sub-fin structure is over a second stack of nanowires, the second stack of nanowires having a greater number of nanowires than the first stack of nanowires, and the second insulator sub-fin structure having a vertical thickness less than a vertical thickness of the first insulator sub-fin structure. A first gate electrode is around the first stack of nanowires, and a second gate electrode is around the second stack of nanowires.

公开(公告)号：EP4099372A1

公开(公告)日：2022-12-07

申请号：EP22171616.0

申请日：2022-05-04

申请人： INTEL Corporation

发明人： GHANI, Tahir ,  WALLACE, Charles ,  GULER, Leonard

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/423

摘要： Conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures. A plurality of dielectric spacers has an uppermost surface co-planar with an uppermost surface of a plurality of gate structures and co-planar with an uppermost surface of a plurality of conductive trench contact structures. A dielectric layer is over the plurality of gate structures, over the plurality of conductive trench contact structures, and over the plurality of dielectric spacers. The dielectric layer has a planar uppermost surface. An opening is in the dielectric layer, the opening exposing one of the plurality of gate structures or one of the plurality of conductive trench contact structures. A conductive via is in the opening. The conductive via has an uppermost surface co-planar with the planar uppermost surface of the dielectric layer.

公开(公告)号：EP4439675A2

公开(公告)日：2024-10-02

申请号：EP23214822.1

申请日：2023-12-07

申请人： INTEL Corporation

发明人： KOH, Shao-Ming ,  MORROW, Patrick ,  MEHTA, Nikhil ,  GULER, Leonard ,  NASKAR, Sudipto ,  DAVIS, Alison ,  LAVRIC, Dan ,  PRINCE, Matthew ,  LUCE, Jeanne ,  WALLACE, Charles ,  VOGELSBERG, Cortnie ,  PAI, Rajaram ,  KILROY, Caitlin ,  AMONOO, Jojo ,  PURSEL, Sean ,  GOTLIB, Yulia

IPC分类号： H01L29/423 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/42376

摘要： Transistor structures comprising a gate electrode, or "gate," that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

公开(公告)号：EP4435841A1

公开(公告)日：2024-09-25

申请号：EP23209725.3

申请日：2023-11-14

申请人： INTEL Corporation

发明人： ALLEN, Gary ,  WALLACE, Charles ,  ENGEL, Clifford ,  GULER, Leonard ,  LIU, Shengsi ,  OBRIEN, Thomas ,  ZHU, Baofu ,  ACHARYA, Saurabh

IPC分类号： H01L21/768 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/7685

摘要： Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.