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    Layout method for dummy structures and corresponding integrated circuit
    1.
    发明公开
    Layout method for dummy structures and corresponding integrated circuit 审中-公开
    布局 - 方法设计师Schaltkreis

    公开(公告)号：EP1505653A1

    公开(公告)日：2005-02-09

    申请号：EP03425532.3

    申请日：2003-08-04

    申请人： STMicroelectronics S.r.l.

    发明人： Cappelletti, Paolo Giuseppe ,  Maurelli, Alfonso ,  Zabberoni, Paola

    IPC分类号： H01L27/115

    CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11546

    摘要： A method for manufacturing electrically non-active structures of an electronic circuit integrated on a semiconductor substrate (5) comprising first electrically active structures (6) and second electrically active structures (7), comprising the steps of:

    inserting, in the electronic circuit, electrically non-active structures (8) to uniform the surface of the electronic circuit, the method being characterised in that it comprises the following further steps:
    identifying, between the electrically non-active structures (8), a first group (9) of electrically non-active structures adjacent to the first (6) and second (7) electrically active structures,
    identifying, between the electrically non-active structures (8), a second group (10) of electrically non-active structures not adjacent to the first (6) and second (7) electrically active structures,
    defining, on the semiconductor substrate, the first (9) and second (10) group of electrically non-active structures through different photolithographic steps.

    摘要翻译： 一种用于制造集成在包括第一电活动结构（6）和第二电活动结构（7）的半导体衬底（5）上的电子电路的电非活性结构的方法，包括以下步骤：在电子电路中， 电非电活动结构（8）以使电子电路的表面均匀，该方法的特征在于其包括以下进一步的步骤：在电非活性结构（8）之间识别第一组（9） 与第一（6）和第二（7）电活性结构相邻的电非活性结构，在电非活性结构（8）之间识别不邻近第一电活性结构（8）的电非活性结构的第二组（10） 第一（6）和第二（7）电活性结构，在半导体衬底上通过不同的光电层限定第一（9）和第二（10）组电非活性结构 书写步骤

    Transistor structure with high input impedance and high current capability and manufacturing process thereof
    4.
    发明公开
    Transistor structure with high input impedance and high current capability and manufacturing process thereof 有权
    晶体管结构具有高输入阻抗，高电流容量及其生产方法

    公开(公告)号：EP1791181A1

    公开(公告)日：2007-05-30

    申请号：EP05425835.5

    申请日：2005-11-25

    申请人： STMicroelectronics S.r.l.

    发明人： Pellizzer, Fabio ,  Cappelletti, Paolo Giuseppe

    IPC分类号： H01L27/07 ,  H01L21/8249 ,  H01L27/24

    CPC分类号： H01L27/24 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/0705

    摘要： Integrated transistor device (10) formed in a chip of semiconductor material (15) having an electrical-insulation region (31) delimiting an active area (30) accommodating a bipolar transistor (11) of vertical type and a MOSFET (12) of planar type, contiguous to one another. The active area accommodates a collector region (18); a bipolar base region (19) contiguous to the collector region; an emitter region (20) within the bipolar base region; a source region (23), arranged at a distance from the bipolar base region; a drain region (24); a channel region (22) arranged between the source region and the drain region; and a well region (35). The drain region (24) and the bipolar base region (19) are contiguous and form a common base structure (19, 24, 37) shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device (10) has a high input impedance and is capable of driving high currents, while only requiring a small integration area.

    摘要翻译： 在具有电绝缘区（31），在有源区（30）限定容纳垂直型的平面的一个双极型晶体管（11）和一个MOSFET（12）的半导体材料的芯片（15）上综合晶体管装置（10） 型，邻接彼此。 有源区可容纳的集电极区域（18）; 双极基极区域（19）邻接所述集电极区; 到发射极双极基极区域内的区域（20）; 一个源极区（23），在从双极基极区域的距离布置; 漏极区（24）; 源区和漏区之间设置的沟道区（22）; 和一个阱区（35）。 漏极区（24）和双极基极区域（19）是连续的，并形成由双极晶体管和MOSFET共有的共有底边结构（19，24，37）。 由此，集成晶体管装置（10）具有高输入阻抗和能够驱动大电流，同时仅需要一个小的积分区。

    Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
    6.
    发明公开
    Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry 有权
    Integrationsverfahren eines Festwertspeichers und eines Hochleistungslogikschaltkreises auf einem Chip

    公开(公告)号：EP1005079A1

    公开(公告)日：2000-05-31

    申请号：EP98830709.6

    申请日：1998-11-26

    申请人： STMicroelectronics S.r.l.

    发明人： Cappelletti, Paolo Giuseppe ,  Maurelli, Alfonso

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

    摘要： A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate (1), forming a first gate oxide layer (3) for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate (1), forming a second gate oxide layer (5) for memory cells of the memory device; on the first and second gate oxide layers (3,5), forming from a first polysilicon layer (6) gate electrodes (8,9) for the first transistors, and floating-gate electrodes (7) for the memory cells; forming over the floating-gate electrodes (7) of the memory cells a dielectric layer (18); on third portions of the semiconductor substrate (1), forming a third gate oxide layer (24) for second transistors operating at the low operating voltage; on the dielectric layer (18) and on the third portions of the semiconductor substrate (1), forming from a second polysilicon layer (25) control gate electrodes (29) for the memory cells, and gate electrodes (26,27) for the second transistors; in the first portions of the semiconductor substrate (1), forming source and drain regions (12,13;16,17) for the first transistors; in the second portions of the semiconductor substrate (1), forming source and drain regions (30,31) for the memory cells; in the third portions of the semiconductor substrate (1), forming source and drain regions for the second transistors.

    摘要翻译： 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入​​式存储器件，其提供：在半导体的第一部分上 衬底（1），形成用于在高工作电压下工作的第一晶体管的第一栅极氧化物层（3） 在所述半导体衬底（1）的第二部分上形成用于所述存储器件的存储器单元的第二栅极氧化物层（5）; 在第一和第二栅极氧化物层（3,5）上形成第一晶体管的第一多晶硅层（6）用于第一晶体管的栅电极（8,9）和用于存储单元的浮栅电极（7）; 在存储单元的浮栅电极（7）上形成介电层（18）; 在半导体衬底（1）的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化物层（24）; 在所述电介质层（18）和所述半导体衬底（1）的所述第三部分上，从第二多晶硅层（25）形成用于存储单元的栅极电极（29）和用于所述存储单元的栅电极（26,27） 第二晶体管; 在半导体衬底（1）的第一部分中，形成用于第一晶体管的源区和漏区（12,13; 16,17） 在半导体衬底（1）的第二部分中，形成用于存储单元的源区和漏区（30,31）; 在半导体衬底（1）的第三部分中，形成用于第二晶体管的源极和漏极区域。