利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1077 条记录 (耗时 0.028 秒)

    A VIRTUAL-GROUND FLASH EPROM ARRAY WITH REDUCED CELL PITCH IN THE X DIRECTION
    92.
    发明公开
    A VIRTUAL-GROUND FLASH EPROM ARRAY WITH REDUCED CELL PITCH IN THE X DIRECTION 失效
    与在X方向上减少细胞的步距虚拟地球FLASH EPROM MATRIX

    公开(公告)号：EP0698286A1

    公开(公告)日：1996-02-28

    申请号：EP95913692.0

    申请日：1995-03-13

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： BERGEMONT, Albert

    IPC分类号： H01L21 ,  H01L27

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

    A SEMICONDUCTOR DEVICE HAVING A SELF-ALIGNED P-WELL WITHIN A P-BURIED-LAYER
    93.
    发明公开
    A SEMICONDUCTOR DEVICE HAVING A SELF-ALIGNED P-WELL WITHIN A P-BURIED-LAYER 失效
    在埋P层自我校正的p SINK HALBLEITERANORNUNG

    公开(公告)号：EP0698283A1

    公开(公告)日：1996-02-28

    申请号：EP95911124.0

    申请日：1995-02-27

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： CHEN, Datong ,  BASHIR, Rashid ,  DE SANTIS, Joseph, A.

    IPC分类号： H01L21

    CPC分类号： H01L21/74 ,  H01L21/823892 ,  H01L21/8249

    摘要： A self-aligned, maskless method of forming a p-well is accomplished by implanting a fast p-type diffuser into a p+ buried layer, prior to epitaxial growth. This way the p-well is self-aligned with the p+ buried layer because one mask is used to define both, and the need for a separate p-well mask is eliminated. The fast diffuser, such as aluminum (Al), diffuses toward the silicon surface during the various thermal steps of the process such as epitaxial growth, field oxidation, sinker diffusion, and final drive-in, etc. The dosage of aluminum used and the parameters of the thermal drive determines the p-well doping level. Similarly, an n-well can also be formed in an n-type buried layer in a self-aligned fashion.

    APPARATUS AND METHOD FOR AUTOMATIC RECOGNITION AND CONFIGURATION OF A PERIPHERAL DEVICE
    94.
    发明公开
    APPARATUS AND METHOD FOR AUTOMATIC RECOGNITION AND CONFIGURATION OF A PERIPHERAL DEVICE 失效
    设备和方法自动检测和外围设备配置

    公开(公告)号：EP0698240A1

    公开(公告)日：1996-02-28

    申请号：EP94916022.0

    申请日：1994-04-28

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： MICHAEL, Martin, S. ,  LEUNG, Frederick, K.

    IPC分类号： G06F13 ,  G06F1 ,  G06F9 ,  G06F15

    CPC分类号： G06F9/4411 ,  G06F13/4068 ,  G06F15/177 ,  G06F2213/0004

    摘要： A computer system includes a peripheral device connector interface that automatically identifies the type of peripheral device, if any, coupled to the interface and configures itself for handling data flows to and from peripheral devices of the identified type. The system includes a connector that receives a number of peripheral identification signals that are generated by a peripheral device attached to the connector. Peripheral device data signals, which are also received at the connector, are routed by a connector interface. A number of interface circuits are provided to control the different types of peripheral devices that may be attached to the connector. The interface circuits are coupled to configuration registers that provide operational information for the interface circuits. A transition detector identifies any change in the peripheral identification signals. Any change in the peripheral identification signals corresponds to a change in the peripheral device attached to the connector. In response to a change peripheral device, an interface disable generator applies a disable signal to the connector interface. A signal decoder is then used to decode the peripheral identification signals so as to identify the peripheral attached to the connector. After the peripheral is identified, configuration data for the peripheral is loaded into the configuration registers.

    Integrated circuit magnetic memory element and method of making same
    95.
    发明公开
    Integrated circuit magnetic memory element and method of making same 失效
    集成电路磁记忆元件及其制造方法

    公开(公告)号：EP0588503A3

    公开(公告)日：1996-02-14

    申请号：EP93306532.8

    申请日：1993-08-18

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Thomas, Michael E. ,  Saadat, Irfan

    IPC分类号： G11C11/00 ,  G11C11/06

    CPC分类号： G11C11/155 ,  G11C11/00

    摘要： Integrated circuit memory elements are fabricated by disposing a first layer of electrically conductive material on the surface of an electrically insulating substrate. The first layer of electrically conductive material is formed into a first predetermined pattern. A second layer of electrically insulating material is disposed on the surface of the electrically insulating substrate and the patterned first layer of electrically conductive material. A first layer of magnetizable material is disposed on the second insulating layer and is formed into a predetermined pattern having a predetermined positional relationship with respect to the underlying patterned first layer of electrically conductive material. A third layer of electrically insulating material is disposed over the second layer of insulating material and the patterned first layer of magnetizable material. Openings are formed in the underlying layers of insulating material to expose predetermined electrical contact areas on the underlying patterned first electrically conductive layer. A second electrically conductive layer is disposed over the third layer of electrically insulating material into the openings and into electrical contact with the exposed electrical contact areas of the underlying patterned first electrically conductive layer. The second electrically conductive layer is formed into a second predetermined pattern having a predetermined positional relationship with respect to the underlying patterned layer of magnetizable material and the patterned first electrically conductive layer. The patterned first electrically conductive layer and the patterned second electrically conductive layer define at least two conductive windings disposed about the patterned magnetizable material.

    Universal asynchronous receiver/transmitter
    96.
    发明公开
    Universal asynchronous receiver/transmitter 失效
    通用异步接收器/发射器

    公开(公告)号：EP0632391A3

    公开(公告)日：1996-01-10

    申请号：EP94115236.5

    申请日：1989-09-08

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Michael, Martin S.

    IPC分类号： G06F13/38 ,  G06F13/28

    CPC分类号： G06F13/382 ,  G06F13/28 ,  G06F13/38 ,  G06F13/385

    摘要： Data characters to be transferred from a peripheral device to a central processing unit are serially shifted into the receiver shift register of a universal asynchronous receiver/transmitter (UART). A multiple byte first-in-first-out memory stores a plurality of data characters received by the shift register. The UART checks the status of each data character stored in the FIFO to determine whether it will trigger an exception. A bytes till exception register indicates the number of data characters remaining in the FIFO until an exception is encountered. Then, upon request by the CPU, the UART provides the count of consecutive valid data characters from the top of the FIFO to the first exception, eliminating the need to check status on every transferred byte. Each of the multiple channels of the UART includes an Initialization Register. Setting the appropriate bit Initialization Register of any UART channel allows concurrent writes to the same selected register in each channel's register set. This function reduces initialization time for all of the common parameters that are loaded into each channel's registers. The UART implements a methodology which allows for the processing of any control characters or errors received by the UART during DMA while internal and/or external FIFOs are being used.

    摘要翻译： 将要从外围设备传输到中央处理单元的数据字符串行移入通用异步接收器/发送器（UART）的接收器移位寄存器。 多字节先进先出存储器存储由移位寄存器接收的多个数据字符。 UART检查存储在FIFO中的每个数据字符的状态，以确定它是否会触发异常。 一个字节直到异常寄存器指示在遇到异常之前剩余在FIFO中的数据字符的数量。 然后，根据CPU的请求，UART提供从FIFO顶部到第一个异常的连续有效数据字符的计数，无需检查每个传输字节的状态。 UART的多个通道中的每一个都包含一个初始化寄存器。 设置任何UART通道的相应位初始化寄存器允许并行写入每个通道寄存器组中相同的选定寄存器。 该函数减少了加载到每个通道寄存器的所有通用参数的初始化时间。 UART实现了一种方法，该方法允许在使用内部和/或外部FIFO的同时处理DMA期间UART接收到的任何控制字符或错误。

    VOLTAGE CONTROLLED OSCILLATOR WITH EFFICIENT PROCESS COMPENSATION
    99.
    发明公开
    VOLTAGE CONTROLLED OSCILLATOR WITH EFFICIENT PROCESS COMPENSATION 失效
    凭借高效的工艺补偿压控OZILLATOR。

    公开(公告)号：EP0682827A1

    公开(公告)日：1995-11-22

    申请号：EP94907929.0

    申请日：1994-01-31

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： JELINEK, Jules, Joseph ,  DENG, Jay

    IPC分类号： H03K3 ,  H03B5 ,  H03L1

    CPC分类号： H03K3/011 ,  H03L1/00

    摘要： A voltage controlled oscillator (VCO) provides an output signal with an output frequency that varies only minimally for any given input control voltage despite variations in the manufacturing process, temperature and supply voltage. The VCO also includes a multistage ring oscillator which includes a plurality of series-connected current-starved inverter stages. The VCO utilizes a first current source to provide a substantially constant current independent of process, temperature and supply voltage and a second current source to provide a variable current that varies in response to process, temperature and supply voltage. Both current sources generate a respective current signal independent of the input signal to the VCO. An attenuator, responsive to the VCO's input voltage signal (typically from a phase-locked loop filter) provides a control current signal to the ring oscillator. The attenuator receives a supply current created by subtracting the second current from the first current, and utilizes a differentiation subcircuit that attenuates the supply current in response to changes in an input voltage to produce a current control signal that sets the current level in the ring oscillator's cells. The frequency of oscillation of the ring oscillator is determined by the control current signal. Additionally, the VCO circuit may include a current mirror for receiving the control current signal from the attenuator and mirroring the control current signal to the ring oscillator.