公开(公告)号：EP2043103A3

公开(公告)日：2009-11-11

申请号：EP08290870.8

申请日：2008-09-16

申请人： Arteris

发明人： Boucard, Philippe ,  Godet, Pascal ,  Montperrus, Luc

IPC分类号： G11C7/10 ,  G11C7/22 ,  G06F12/08

CPC分类号： G11C7/1039 ,  G06F12/0893 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C2207/104 ,  G11C2207/2245

摘要： Un dispositif de mémoire électronique comporte un banc de mémoires (102) muni d'un cache (104), un séquenceur pour assurer les accès physiques audit banc de mémoires (102), une interface physique (110) pour recevoir des requêtes d'accès mémoire de haut niveau, un gestionnaire de requêtes (108) entre l'interface physique (110) et le séquenceur(106), lequel gestionnaire de requêtes (108) comprend une file d'attente d'entrée (114) pour stocker les requêtes d'accès mémoire de haut niveau et une fonction d'arbitrage (116) qui tient compte de données du cache (104) et de données de la file d'attente d'entrée (114) pour désigner une requête à exécuter, permettant de réaliser le banc de mémoires (102), le séquenceur (106) et le gestionnaire de requêtes (108) sur une puce unique, l'interface physique assurant la connexion avec l'extérieur de la puce.

公开(公告)号：EP1573270A4

公开(公告)日：2009-07-22

申请号：EP03812914

申请日：2003-12-09

申请人： MICRON TECHNOLOGY INC

发明人： JOHNSON CHRISTOPHER S ,  JOHNSON BRIAN

IPC分类号： G11C7/10 ,  G01C3/00

CPC分类号： G11C7/1087 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

摘要： A logic circuit (110) operates write receivers in a dynamic random access memory device (20, 22) in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit (110) receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit (110) maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.

公开(公告)号：EP2002447A2

公开(公告)日：2008-12-17

申请号：EP07758464.7

申请日：2007-03-13

申请人： Sandisk Corporation

发明人： CERNEA, Raul-Adrian

IPC分类号： G11C29/00 ,  G11C16/26

CPC分类号： G11C7/106 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C16/04 ,  G11C29/846

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.

公开(公告)号：EP1818831B1

公开(公告)日：2008-11-12

申请号：EP07108400.8

申请日：2003-06-27

申请人： Fujitsu Ltd.

发明人： Fujioka, Shinya ,  Sato, Kotoku ,  Ikeda, Hitoshi ,  Okuyama, Yoshiaki ,  Ohno, Jun

IPC分类号： G06F12/08 ,  G11C16/16

CPC分类号： G11C7/20 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4093 ,  G11C16/10 ,  G11C2211/4067 ,  G11C2211/4068

公开(公告)号：EP1535162A4

公开(公告)日：2007-01-24

申请号：EP03817282

申请日：2003-06-26

申请人： RAMBUS INC

发明人： PEREGO RICHARD E ,  STARK DONALD C ,  WARE FREDERICK A

IPC分类号： G06F12/04 ,  G06F12/06 ,  G11C5/00 ,  G11C5/04 ,  G11C7/10 ,  G11C8/00 ,  G11C11/408 ,  G11C11/4097 ,  H05K1/11 ,  H05K1/14 ,  G06F12/08

CPC分类号： G06F13/1678 ,  G06F12/04 ,  G06F12/06 ,  G06F12/0646 ,  G06F13/1657 ,  G06F13/4022 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1087 ,  G11C8/06 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/105 ,  G11C2207/108 ,  H05K1/117 ,  H05K1/14 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y02D10/14

摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

摘要翻译： 描述了存储器系统，其中存储器核心组织随设备宽度而变化。 访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。 增加用于窄内存宽度的逻辑存储器组的数量减少了存储体冲突的可能性，从而提高了速度性能。

公开(公告)号：EP1246388A3

公开(公告)日：2006-06-07

申请号：EP01308894.3

申请日：2001-10-19

申请人： FUJITSU LIMITED

发明人： Saze, Takuya, c/o Fujitsu Limited ,  Tamura, Hirotaka, c/o Fujitsu Limited ,  Chiba, Takaya, Fujitsu Higashi-Nihon Dig.Tech.Ltd. ,  Gotoh, Kohtaroh, c/o Fujitsu Limited ,  Ishida, Hideki, c/o Fujitsu Limited

IPC分类号： H04L7/033 ,  G06F1/12 ,  H04J3/04

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/091 ,  H04L7/033 ,  H04L7/0337

摘要： A clock recovery circuit has a boundary detection/discrimination circuit (21 to 24) to detect and discriminate a boundary in an input signal (DIL) in accordance with a first signal (CLKb). The clock recovery circuit performs clock recovery by controlling the timing of the first signal (CLKb) in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit (21 to 24) is varied by controlling the first signal (CLKb).

公开(公告)号：EP1642297A1

公开(公告)日：2006-04-05

申请号：EP04777804.8

申请日：2004-07-07

申请人： MICRON TECHNOLOGY, INC.

发明人： MORZANO, Christopher, K. ,  LI, Wen

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4094

摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

公开(公告)号：EP0833342A3

公开(公告)日：2005-10-26

申请号：EP97307182.2

申请日：1997-09-16

申请人： International Business Machines Corporation

发明人： Watanabe, Shinpei ,  Sunaga, Toshio

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4096

摘要： A DRAM system that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order so that a seamless operation is assured not only for reading but also for writing. A prefetch mechanism is used for reading and writing data to a separate memory array at an early stage, so that the activation and precharge operation, which must be performed before reading the next set of data from the memory array, does not affect nor cause any deterioration of access speed. The amount of data prefetched is twice as much as that fetched in the period represented by an array time constant so that in a single bank structure a seamless operation can be performed both for reading and for writing, even when row accesses are performed.

公开(公告)号：EP1485919A2

公开(公告)日：2004-12-15

申请号：EP03714158.7

申请日：2003-03-13

申请人： INTEL CORPORATION

发明人： KURUPATI, Sreenath

IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C11/408

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4093

摘要： A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

公开(公告)号：EP1474805A2

公开(公告)日：2004-11-10

申请号：EP03739677.7

申请日：2003-01-23

申请人： MICRON TECHNOLOGY, INC.

发明人： KEETH, Brent

IPC分类号： G11C7/10

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2254

摘要： Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data corrector uses differential clock signals and a reference voltage to generate the set of adjustment vectors to be provided to the data receivers. The data receiver is an improved receiver incorporating a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point relative to the reference voltage.