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    Semiconductor integrated circuit device
    1.
    发明公开
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：EP1739517A2

    公开(公告)日：2007-01-03

    申请号：EP06017381.2

    申请日：2003-07-04

    申请人： FUJITSU LIMITED

    发明人： Ishida, Hideki, c/o Fujitsu Limited ,  Oono, Megumi, c/o Fujitsu Limited

    IPC分类号： G05F3/26 ,  H03F3/45

    CPC分类号： G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

    摘要： Semiconductor integrated circuit device having an amplifier unit (20) which receives input signals and is constituted by high-voltage MIS transistors of a first conductivity type and a second conductivity type, and a level-shifting unit (50) which receives the output from said amplifier unit and produces a signal of a level that is shifted, wherein said amplifier unit comprises diode-connected high-voltage MIS transistors (221,222) of the second conductivity type; and said level-shifting unit comprises high-voltage MIS transistors (35,36) of the second conductivity type current mirror-connected to said diode-connected high-voltage MIS transistors of the second conductivity type, as well as low-voltage MIS transistors of the first conductivity type (28,31) and of the second conductivity type (37,39).

    摘要翻译： 半导体集成电路器件，具有接收输入信号并由第一导电类型和第二导电类型的高压MIS晶体管构成的放大器单元（20）;以及电平移位单元（50），接收来自所述 放大器单元并且产生被移位的电平的信号，其中所述放大器单元包括第二导电类型的二极管连接的高压MIS晶体管（221,222） 并且所述电平移位单元包括与第二导电类型的所述二极管连接的高压MIS晶体管镜像连接的第二导电类型电流的高压MIS晶体管（35,36），以及低压MIS晶体管 的第一导电类型（28,31）和第二导电类型（37,39）。

    Automatic bias adjustment circuit for use in PLL circuit
    3.
    发明公开
    Automatic bias adjustment circuit for use in PLL circuit 有权
    用于设定工作点锁相环电路自动电路

    公开(公告)号：EP1223676A2

    公开(公告)日：2002-07-17

    申请号：EP01309826.4

    申请日：2001-11-22

    申请人： FUJITSU LIMITED

    发明人： Higashi, Hirohito, c/o Fujitsu Limited ,  Ishida, Hideki, c/o Fujitsu Limited

    IPC分类号： H03L7/099

    CPC分类号： H03L7/0805 ,  H03L1/022 ,  H03L7/0893 ,  H03L7/10 ,  H03L7/189

    摘要： A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is opposite to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.

    Semiconductor integrated circuit device
    6.
    发明公开
    Semiconductor integrated circuit device 有权
    Halbleiter integrierte Schaltungsvorrichtung

    公开(公告)号：EP1385075A2

    公开(公告)日：2004-01-28

    申请号：EP03254251.6

    申请日：2003-07-04

    申请人： FUJITSU LIMITED

    发明人： Ishida, Hideki, c/o Fujitsu Limited ,  Oono, Megumi, c/o Fujitsu LSI Technology Ltd.

    IPC分类号： G05F3/26 ,  H03F3/345 ,  H03F3/45

    CPC分类号： G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

    摘要： A semiconductor integrated circuit device has a first MIS transistor (3) of a first conductivity type, a second MIS transistor (8) of a second conductivity type, a resistor (9) connected in series between a first power-source line and a second power-source line, and a third MIS transistor (4) of the first conductivity type. The third MIS transistor has a gate connected to a node (N4) where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node (N1) where the second MIS transistor (8) and the resistor (9) are connected together.

    摘要翻译： 半导体集成电路器件具有第一导电类型的第一MIS晶体管（3），第二导电类型的第二MIS晶体管（8），串联连接在第一电源线和第二导电类型之间的电阻器 电源线和第一导电类型的第三MIS晶体管（4）。 第三MIS晶体管具有连接到第一MIS晶体管和第二MIS晶体管连接在一起的节点（N4）的栅极，以及连接到连接节点（N1）的漏极，其中第二MIS晶体管（8）和电阻器 （9）连接在一起。

    Semiconductor integrated circuit device
    10.
    发明公开
    Semiconductor integrated circuit device 有权

    公开(公告)号：EP1739517A3

    公开(公告)日：2007-01-10

    申请号：EP06017381.2

    申请日：2003-07-04

    申请人： FUJITSU LIMITED

    发明人： Ishida, Hideki, c/o Fujitsu Limited ,  Oono, Megumi, c/o Fujitsu Limited

    IPC分类号： G05F3/26 ,  H03F3/45

    CPC分类号： G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

    摘要： Semiconductor integrated circuit device having an amplifier unit (20) which receives input signals and is constituted by high-voltage MIS transistors of a first conductivity type and a second conductivity type, and a level-shifting unit (50) which receives the output from said amplifier unit and produces a signal of a level that is shifted, wherein said amplifier unit comprises diode-connected high-voltage MIS transistors (221,222) of the second conductivity type; and said level-shifting unit comprises high-voltage MIS transistors (35,36) of the second conductivity type current mirror-connected to said diode-connected high-voltage MIS transistors of the second conductivity type, as well as low-voltage MIS transistors of the first conductivity type (28,31) and of the second conductivity type (37,39).