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2021 条记录 (耗时 0.024 秒)

    Backdrive protection circuit
    91.
    发明公开
    Backdrive protection circuit 审中-公开
    Schutzschaltung gegenRückströme

    公开(公告)号：EP2503690A2

    公开(公告)日：2012-09-26

    申请号：EP12159384.2

    申请日：2012-03-14

    申请人： NXP B.V.

    发明人： Koellmann, Andreas

    IPC分类号： H03K17/082 ,  H03K17/16 ,  H03K19/003

    CPC分类号： H03K17/302

    摘要： Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node (output) of the device and includes circuitry (104,106) that is configured to compare the supply voltage node (VDD_IN) and the output node (output). In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches (108,110) are used to place the device (112) in different modes in response to the output signal.

    摘要翻译： 提供了方法，装置和电路以防止反向驱动电流。 一个这样的设备经受来自设备的输出节点（输出）的反向电压，并且包括被配置为比较电源电压节点（VDD_IN）和输出节点（输出）的电路（104,106）。 响应于比较，电路产生输出信号。 输出信号的电平转换版本用于提供对应于电源电压节点和输出节点的较高者的输出电压。 开关（108,110）用于响应于输出信号将设备（112）放置在不同的模式中。

    Output circuit, system including output circuit, and method of controlling output circuit
    92.
    发明公开
    Output circuit, system including output circuit, and method of controlling output circuit 有权
    输出电路系统，用于控制所述输出电路的输出电路和方法

    公开(公告)号：EP2487795A2

    公开(公告)日：2012-08-15

    申请号：EP12151674.4

    申请日：2012-01-19

    申请人： Fujitsu Semiconductor Limited

    发明人： Miyazaki, Hiroshi

    IPC分类号： H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00361 ,  H03K19/018507

    摘要： An output circuit (34) includes a first transistor (T1) coupled to an external terminal (P2) and having a gate terminal that receives a first drive signal (S5). The first transistor (T1) drives a potential at the external terminal (P2) in accordance with the first drive signal (S5). The output circuit (34) also includes a capacitor (C1). The capacitor (C1) includes a first end coupled to the gate terminal of the first transistor (T1). A clamp circuit (46) clamps a second end of the capacitor (C1) to a potential corresponding to the operation of the first transistor (T1).

    摘要翻译： 一个输出电路（34）包括联接到在外部端子（P2）的第一晶体管（T1）和具有栅极端子做接收第一驱动信号（S5）。 第一晶体管（T1）驱动在雅舞蹈外部端子（P2）与所述第一驱动信号（S5）的电位。 因此，输出电路（34）包括电容器（C1）。 电容器（C1）包括第一端耦合到所述第一晶体管（T1）的栅极端子。 钳位电路（46）夹住电容器（C1）到一个潜在的对应于所述第一晶体管（T1）的外科手术的第二端。

    ELEKTRISCHE SCHALTUNG ZUR ÜBERTRAGUNG VON SIGNALEN ZWISCHEN ZWEI MASTERN UND EINEM ODER MEHREREN SLAVES
    93.
    发明公开
    ELEKTRISCHE SCHALTUNG ZUR ÜBERTRAGUNG VON SIGNALEN ZWISCHEN ZWEI MASTERN UND EINEM ODER MEHREREN SLAVES 有权
    电路FOR信号之间的两个主人和一个或多个从传输

    公开(公告)号：EP2452436A1

    公开(公告)日：2012-05-16

    申请号：EP10730151.7

    申请日：2010-07-01

    申请人： Robert Bosch GmbH

    发明人： FRESE, Volker

    IPC分类号： H03K19/0175 ,  G06F13/40 ,  G06F13/364 ,  H03K19/003

    CPC分类号： H03K19/003 ,  G06F13/364 ,  G06F13/4072 ,  H03K19/017509 ,  H03K19/01759

    摘要： The invention relates to an electrical circuit (10) for transmitting signals between two masters (11, 12) and one or more slaves (13, 14). The two masters (11, 12) and the slave or slaves (13, 14) are interconnected by means of a bus system (15). At least one master data signal (MO) can be generated by each of the two masters (11, 12) and can be received by the slave or slaves (13, 14). A tri-state gate (16) is present at the outputs of the two masters (11, 12) at which the respective master data signal (MO) is present. The tri-state gates (16) act either as closed or as opened switches. The tri-state gates (16) are actuated such that tri-state gate (16
    11 ) associated with one of the two masters (11) acts as a closed switch and the tri-state gate (16
    12 ) associated with the other of the two masters (12) acts as an opened switch.

    Configurable power switch cells and methodology
    94.
    发明公开
    Configurable power switch cells and methodology 有权
    Konfigurierbare Leistungsschalterzellen und Methode

    公开(公告)号：EP2429079A2

    公开(公告)日：2012-03-14

    申请号：EP11179367.5

    申请日：2011-08-30

    申请人： Apple Inc.

    发明人： Suzuki, Shingo ,  Lamburn, Robert E. ,  Jandhyala, Neehar

    IPC分类号： H03K19/00 ,  H03K19/003 ,  G06F17/50

    CPC分类号： H03K19/0016 ,  G06F17/5072 ,  G06F2217/78 ,  H03K19/00346

    摘要： In one embodiment, a configurable power switch cell methodology may include designing multiple power switch cells which may be assembled to form a set of power switches such as a power switch segment (20A-20E). The power switch cells may all be designed to occupy the same amount of integrated circuit area, in an embodiment. Accordingly, one cell may be readily replaced by another, even late in the design process, without disturbing the placement of surrounding circuitry. In an embodiment, the power switch cells may include the interconnect layers that connect between cells, and abutting the power switch cells may automatically connect the interconnect between cells. Accordingly, swapping one power switch cell for another may be accomplished by placing the cell. No routing work may be required.

    摘要翻译： 在一个实施例中，可配置电力开关单元方法可以包括设计多个功率开关单元，所述多个功率开关单元可以组装以形成诸如功率开关段（20A-20E）的一组功率开关。 在一个实施例中，功率开关单元可以全部设计成占据相同量的集成电路面积。 因此，一个电池可以容易地被替换，甚至在设计过程的后期，而不会扰乱周围电路的放置。 在一个实施例中，功率开关单元可以包括在单元之间连接的互连层，并且邻接功率开关单元可以自动地连接单元之间的互连。 因此，将一个电源开关单元互换为另一个可以通过放置电池来实现。 不需要路由工作。

    A simple self-adjusting overvoltage-protection circuit for low voltage CMOS input and output interface circuits with high voltage tolerance and with full rail-to-rail bidirectional voltage levels
    98.
    发明公开
    A simple self-adjusting overvoltage-protection circuit for low voltage CMOS input and output interface circuits with high voltage tolerance and with full rail-to-rail bidirectional voltage levels 审中-公开
    用于低电压CMOS输入和Ausgabeschnitstellenschaltungen高电压耐受性和与双向总线的电压电平的简单的自调整浪涌保护电路

    公开(公告)号：EP2326008A1

    公开(公告)日：2011-05-25

    申请号：EP10191400.0

    申请日：2010-11-16

    申请人： NXP B.V.

    发明人： Mann, Allen James ,  Mahooti, Kevin

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00315

    摘要： A modified CMOS switch (402), composed of parallel N-channel (410) and P-channel (412) transistors, is placed between the pad (14) and the input buffer and/or output devices (404). The applied pad voltage relative to V DD determines the configuration of the switch (402), and also, the P-channel floating-well bias-voltage (nw). For the applied pad voltage above V DD , only the N-channel device (410) is on and the P-channel device (412,414) is off. In this configuration the N-channel limits the input voltage on the buffer side to (V DD -V TN ), and therefore, acts as the over-voltage protection device. For pad voltages at and below V DD , both the N-channel (410) and the P-channel devices (414) are on, and the voltage-levels on both sides of the protection structure are the same.

    摘要翻译： 一种改进的CMOS开关（402）平行的N沟道（410）和P沟道（412）晶体管构成，在所述垫（14）和输入缓冲器和/或输出设备（404）之间放置。 施加焊盘电压相对于V DD确定性地雷所述开关（402）的配置，并且因此，P沟道浮阱偏压电压（NW）。 对于上面的VDD应用焊盘电压，只有在N沟道器件（410）是和P沟道器件（412.414）是关闭的。在这种结构中的N信道限制在缓冲侧到输入电压（V DD -V TN），并且因此，作为过电压保护装置。 在和低于VDD无论是N沟道（410）和P沟道器件（414）衬垫的电压导通，并且在所述保护结构的bothsides电压电平相同。