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11.发明公开Programmable protocol processing engine for network packet devices 审中-公开Netzwerkpaketvorrichtung计划工程师
公开(公告)号：EP1267543A2
公开(公告)日：2002-12-18
申请号：EP01127402.4
申请日：2001-11-23
发明人： Jha, Pankaj K.
CPC分类号： H04L49/9094 , H04L29/06 , H04L49/90 , H04L49/901 , H04L69/08 , H04L69/18
摘要： A circuit generally comprising a database and a processing circuit. The database may be configured to store a pointer for each first parameter of a network protocol. The processing circuit may be configured to (i) process at least one of the first parameters in an incoming packet in accordance with the pointer to produce a second parameter and (ii) present an outgoing packet containing the second parameter.
摘要翻译： 通常包括数据库和处理电路的电路。 数据库可以被配置为存储针对网络协议的每个第一参数的指针。 处理电路可以被配置为（i）根据指针处理输入分组中的第一参数中的至少一个以产生第二参数，并且（ii）呈现包含第二参数的输出分组。
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公开(公告)号：EP1266474A2
公开(公告)日：2002-12-18
申请号：EP01916488.8
申请日：2001-03-08
发明人： GREEN, Gary, W.
IPC分类号： H04K1/00
摘要： An apparatus (figures 2 and 3) that may be configured to generate a wireless radio signal in response to one or more first data signals. The warless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices (104a-104n). The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.
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公开(公告)号：EP0718847A3
公开(公告)日：1997-07-02
申请号：EP95308379.7
申请日：1995-11-22
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： A single ended dual port memory cell is described. A bit of data received from one of the first and second ports can be stored. Each of the first and second ports can simultaneously detect the stored bit. A method of reading the contents of a dual port memory cell which has a Beta Ratio less than 1.5 is also described. A wordline is associated with a selected port of the memory cell. The wordline is coupled to a gate device of the memory cell for controlling communication between the memory cell and a bitline. The gate device has a first conductance at a first wordline voltage and a second conductance at a second wordline voltage. The second conductance is less than the first conductance. A port of the cell is selected by applying a select voltage to the associated wordline. The select voltage is approximately the same as the second wordline voltage. The cell contents are then retrieved from the bitline.
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公开(公告)号：EP0357213B1
公开(公告)日：1994-09-07
申请号：EP89307499.7
申请日：1989-07-24
CPC分类号： H03K19/17712 , G05F3/245 , G11C16/26 , H03K5/04 , H03K19/0016
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公开(公告)号：EP2458756A3
公开(公告)日：2018-01-10
申请号：EP11179428.5
申请日：2011-08-30
发明人： Suina, Kenji , Arai, Takashi , Mita, Koichi , Shimamura, Akira , Ishikawa, Hidetoshi , Moriya, Takashi , Nozawa, Yuuki , Kondo, Hideki
CPC分类号： H04W56/001 , H04J3/0652 , H04L12/417
摘要： A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop.
摘要翻译： 节点系统包括第一节点，第二节点和监控节点，其在增加或减少周期微尖刺计数的同时传输帧，并且通过从周期微尖刺计数中减去或添加速率校正极限值来确定缩短周期微尖刺计数 当第一节点停止发送时，由第一节点发送的第一帧的接收停止，并且管理节点的周期性微小吸取计数停止。
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公开(公告)号：EP2999120A2
公开(公告)日：2016-03-23
申请号：EP15180433.3
申请日：2015-08-10
发明人： THIAGARAJAN, Eashwar , KUTZ, Harold , KLEIN, Hans , JOHAL, Jaskam Singh , VANITEGEM, Jean-Paul , CASTOR-PERRY, Kendall , HASTINGS, Mark , RICHARDSON, Amsby , PAI MAROOR, Anasuya , KHAN, Ata , SEGUINE, Dennis , BYRKETT, Bruce , LIEPOLD, Carl , VAN ANTWERPEN, Hans
CPC分类号： H03K19/017581 , H03K19/0005 , H03K19/00346 , H03K19/02 , H03M1/1205 , H03M1/38
摘要： An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.
摘要翻译： 集成电路（IC）装置可以包括多个模拟块，包括至少一个固定功能模拟电路和至少一个可重新配置的模拟电路块，所述至少一个可重配置模拟电路块选自：包括多个可重新配置的放大器电路的连续时间（CT） 离散时间块，包括具有可重新配置的交换网络的放大器; 模拟多路复用器（MUX）被配置为选择性地将IC器件的多个输入/输出（I / O）中的任何一个连接到模拟块，模拟MUX包括至少一个具有比其他电阻低的低噪声信号路径对 模拟MUX的信号路径; 至少一个模拟路由块可重新配置以在任何模拟块之间提供信号路径; 包括数字电路的数字部分; 以及耦合到模拟块的处理器接口。
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17.发明公开ENCRYPTION METHOD FOR EXECUTE-IN-PLACE MEMORIES 审中-公开VERSCHLÜSSELUNGSVERFAHRENZUR AUSFHHRUNG VON XIP-SPEICHERN
公开(公告)号：EP2958264A1
公开(公告)日：2015-12-23
申请号：EP15171989.5
申请日：2015-06-12
CPC分类号： G06F21/80 , G06F9/44573 , G06F12/1408 , G06F21/79 , G09C1/00 , H04L9/0637 , H04L2209/12
摘要： Encryption/decryption techniques for external memory are described herein. In an example embodiment, a device comprises an internal memory and an external memory controller. The internal memory is configured to store a key. The external memory controller is configured to encrypt, with the key, an address for an access operation to an external memory device to obtain an encrypted address, and to encrypt or decrypt a block of data for the access operation based on the encrypted address.
摘要翻译： 本文描述了用于外部存储器的加密/解密技术。 在示例实施例中，设备包括内部存储器和外部存储器控制器。 内部存储器配置为存储一个密钥。 外部存储器控制器被配置为利用密钥加密用于对外部存储器设备的访问操作的地址以获得加密地址，并且基于加密的地址来加密或解密用于访问操作的数据块。
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公开(公告)号：EP2859431A1
公开(公告)日：2015-04-15
申请号：EP13803634.8
申请日：2013-06-04
发明人： TATE, Daniel , SLEZINSKYY, Oleh , YAROSH, Andriy
IPC分类号： G06F3/041
摘要： Apparatuses and methods of glove touch detection are described. One method performs a first scan to detect an object proximate to a sense array. The first scan comprises a first sensitivity parameter. The method compares touch data from the first scan against a plurality of thresholds. The method performs a second scan to detect a touch event when the first scan's touch data exceeds a glove saturation threshold of the plurality of thresholds. The second scan comprising a second sensitivity parameter that is different than the first sensitivity parameter. The method reports a glove touch event when the first scan's touch data does not exceed the glove saturation threshold and exceeds a glove-reporting threshold of the plurality of thresholds.
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公开(公告)号：EP2831917A1
公开(公告)日：2015-02-04
申请号：EP13767422.2
申请日：2013-03-15
发明人： LEVY, Sagy , RAMKUMAR, Krishnaswamy , JENNE, Fredrick , GEHA, Sam
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L27/11582 , H01L29/0673 , H01L29/0676 , H01L29/42348 , H01L29/513 , H01L29/518 , H01L29/66439 , H01L29/66833 , H01L29/775 , H01L29/785 , H01L29/7926
摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的通道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氧氮化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接沟道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。
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公开(公告)号：EP2831916A1
公开(公告)日：2015-02-04
申请号：EP13767277.0
申请日：2013-03-08
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L27/11582 , H01L29/0673 , H01L29/0676 , H01L29/42348 , H01L29/513 , H01L29/518 , H01L29/66439 , H01L29/66833 , H01L29/775 , H01L29/785 , H01L29/7926
摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
摘要翻译： 描述了包括分离电荷俘获区域的非平面存储器件的实施例及其形成方法。 通常，该器件包括：由覆盖连接存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 覆盖所述隧道氧化物的分离电荷俘获区域，所述分离电荷俘获区域包括底部电荷俘获层和顶部电荷俘获层，所述底部电荷俘获层包括更靠近所述隧道氧化物的氮化物，其中所述底部电荷俘获层被分离 从顶部电荷俘获层通过包含氧化物的薄反隧道层。 其他实施例也被公开。
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