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    HARDWARE SECURE MODULE, RELATED PROCESSING SYSTEM, INTEGRATED CIRCUIT, DEVICE AND METHOD
    13.
    发明公开
    HARDWARE SECURE MODULE, RELATED PROCESSING SYSTEM, INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3425552A1

    公开(公告)日：2019-01-09

    申请号：EP18178541.1

    申请日：2018-06-19

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

    Inventor： COLOMBO, Roberto ,  BERTONI, Guido Marco ,  ORLANDO, William ,  VITTIMANI, Roberta

    IPC: G06F21/72 ,  G06F21/60 ,  G06F21/76

    Abstract: A hardware secure module (HSMa) is described. The hardware secure module (HSMa) comprises a processing unit (106b) and a cryptographic coprocessor (106c). The cryptographic coprocessor (106c) comprises a key storage memory (1064) for storing at least one cryptographic key (MK, CK), a first interface (1068) configured to receive source data (SD) to be processed, a hardware crypto engine (1066) configured to process the source data (SD) as a function of at least one cryptographic key (MK, CK) stored in the key storage memory (1064), a second interface (1060) configured to receive a first cryptographic key (CK) from the processing unit (106b), and a hardware key management circuit (1074) configured to store the first cryptographic key (CK) in the key storage memory (1064).
    In particular, the cryptographic coprocessor (106c) comprises a third interface (1070) configured to receive a second cryptographic key (MK), wherein the hardware key management circuit (1074) is configured to store the second cryptographic key (MK) in the key storage memory (1064). The hardware secure element (HSMa) comprises a non-volatile memory (110) adapted to store the second cryptographic key (MK), and a hardware configuration module (106d) configured to read the second cryptographic key (MK) from the non-volatile memory (110) and send the second cryptographic key (MK) to the second interface (1060).

    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    15.
    发明公开
    PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP3413195A1

    公开(公告)日：2018-12-12

    申请号：EP18173959.0

    申请日：2018-05-24

    Applicant: STMicroelectronics Application GmbH

    Inventor： COLOMBO, Roberto

    IPC: G06F9/445

    Abstract: A processing system is described. The processing system comprises a processing unit (102) and at least one configuration data client (112), each configuration data client (112) comprising a register, wherein each configuration data client (112) is configured to receive configuration data (CD) and store the configuration data (CD) received in the respective register. At least one hardware block is configured to change operation as a function of the configuration data (CD) stored in the registers of the at least one configuration data client (112). Specifically, a non-volatile memory (104) comprises the configuration data (CD), and a hardware configuration module (108) is configured to read the configuration data (CD) from the non-volatile memory (104) and transmit the configuration data (CD) to the at least one configuration data client (112).
    Specifically, the hardware configuration module (108) is configured to:
    - receive a command (CMD) from the processing unit (102), wherein the command (CMD) comprises an access request to the configuration data stored in the register of one of the at least one configuration data client (112); and
    - selectively execute the access request.

    PROCESSING SYSTEM, RELATED DEVICE AND METHOD FOR PROTECTING LATCHES OR FLIP-FLOPS OF A REGISTER
    18.
    发明公开
    PROCESSING SYSTEM, RELATED DEVICE AND METHOD FOR PROTECTING LATCHES OR FLIP-FLOPS OF A REGISTER 审中-公开

    公开(公告)号：EP4187415A1

    公开(公告)日：2023-05-31

    申请号：EP22205161.7

    申请日：2022-11-02

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

    Inventor： ZARGAR, Asif Rashid ,  GROSSIER, Nicolas Bernard ,  JAIN, Charul ,  COLOMBO, Roberto

    IPC: G06F21/44 ,  G06F21/55 ,  G06F21/76 ,  G06F21/79 ,  G06F21/85

    Abstract: A processing system (10a) is described. The processing system (10a) comprises a plurality of storage elements (113), wherein each storage element (113) is configured to receive a write request comprising a data bit (DATA) and store the received data bit (DATA) to a latch or flip-flop (1122). A hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation as a function of the logic level stored to the latch or flip-flop (1122) of a first storage element (113) of the plurality of storage elements (113). A non-volatile memory (104; 126) is configured to store data bits (CD, LCD) for the plurality of storage elements (113) and a hardware configuration circuit (108) is configured to read the data bits from the non-volatile memory (104; 126) and generate write requests in order to store the data bits to the storage elements (113).
    Specifically, the hardware circuit (110, 150, 152, 1130, 1502) is configured to change operation also as a function of the first tamper signal (TAMP). For this purpose, the first storage element (113) comprises a further latch or flip-flop (1124) and is configured to store, in response to the write request, the inverted version (1126) of the received data bit to the further latch or flip-flop (1124). The first storage element (113) comprises also a combinational logic circuit (1128) configured to compare the logic level stored to the latch or flip-flop (1122) of the first storage element (113) with the logic level stored to the further latch or flip-flop (1122) of the first storage element (113). The combinational logic circuit (1128) is configured to de-assert a first tamper signal (TAMP) associated with the first storage element (113) when the logic levels are different, and assert the first tamper signal (TAMP) when the logic levels are the same.

    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
    19.
    发明公开
    A PROCESSING SYSTEM COMPRISING A QUEUED SERIAL PERIPHERAL INTERFACE, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD 审中-公开

    公开(公告)号：EP4152171A1

    公开(公告)日：2023-03-22

    申请号：EP22206499.0

    申请日：2021-03-12

    Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

    Inventor： NANDLINGER, Rolf ,  OLEXA, Radek

    IPC: G06F13/40

    Abstract: A processing system (10a) comprising a queued Serial Peripheral Interface, SPI, circuit (30a) is described. The SPI circuit (30a) comprises a hardware SPI communication interface (36), an arbiter (34) and a plurality of interface circuits (32 0 ..32 n ). Specifically, each interface circuit (32 0 ..32 n ) comprises a transmission FIFO memory (320), a reception FIFO memory (322) and an interface control circuit (324). The interface control circuit (324) is configured to receive one or more first data packets from a digital processing circuit (102) and store the received one or more first data packets to the transmission FIFO memory (320). Next, the interface control circuit (324) sequentially reads the one or more first data packets from the transmission FIFO memory (320), extracts from the one or more first data packets at least one transmission data word (DATA), and provides the at least one extracted transmission data word (DATA) to the arbiter (34). In turn, interface control circuit (324) receives from the arbiter (34) a reception data word (RXDATA) and stores one or more second data packets to the reception FIFO memory (322), the one or more second data packets comprising the received reception data word (RXDATA). Finally, the interface control circuit (324) sequentially reads the one or more second data packets from the reception FIFO memory (322) and transmits the one or more second data packets to the digital processing circuit (102).

    A PROCESSING SYSTEM FOR MONITORING THE CELL VOLTAGES OF A RECHARGEABLE BATTERY, RELATED BATTERY MONITORING SYSTEM AND ELECTRIC VEHICLE
    20.
    发明公开
    A PROCESSING SYSTEM FOR MONITORING THE CELL VOLTAGES OF A RECHARGEABLE BATTERY, RELATED BATTERY MONITORING SYSTEM AND ELECTRIC VEHICLE 审中-公开

    公开(公告)号：EP3944457A1

    公开(公告)日：2022-01-26

    申请号：EP21185551.5

    申请日：2021-07-14

    Applicant: STMicroelectronics Application GmbH

    Inventor： EKLER, Markus

    IPC: H02J7/00 ,  H01M10/48 ,  H03M7/30 ,  B60L58/10 ,  H01M10/42

    Abstract: A processing system (44a) configured to monitor the cell voltages of a given number (n) of cells of a rechargeable battery is described. The processing system (44a) comprises terminals (CP 0 ..CP n ) configured to be connected to the cells in order to receive the cell voltages, at least one analog to digital converter (448) is configured to generate digital samples of the cell voltages. The processing system (44a) comprises also a digital processing circuit (444a), a serial communication interface (440) and a transmission queue (452) used to interface the digital processing circuit (444a) with the serial communication interface (440), whereby the serial communication interface (440) and the digital processing circuit (444a) may operate in parallel. Specifically, the digital processing circuit (444a) is configured to synchronously acquire a given number (k) of digital samples (S 1,1 ..S n,k ) of each of the given number (n) of cell voltages and store the acquired digital samples (S 1,1 ..S n,k ) to a memory (DATA). Next, the digital processing circuit (444a) encodes the digital samples (S 1,1 ..S n,k ) stored to the memory (DATA) via a data compression module (450), thereby generating encoded data, and stores the encoded data to the transmission queue (452).
    For example, the data compression module (450) may be configured to generate the encoded data by means of a dynamic range reduction operation (2004), wherein the data compression module (450) subtracts a given offset ( OFF ) from each digital sample (S 1,1 ..S n,k ), thereby generating values indicative of the dynamic variation of each sample with respect to the offset ( OFF ) , and removes a given number of most significant bits from each values. Preferably the given offset ( OFF ) is programmable.

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