公开(公告)号：EP0693217B1

公开(公告)日：2000-05-10

申请号：EP95908799.0

申请日：1995-02-02

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E.

IPC分类号： G11C11/34 ,  G11C16/04 ,  H03K19/177

CPC分类号： G11C14/00 ,  G11C14/0063

摘要： A non-volatile, low, and zero power, high speed self-sensing programmable device and architecture including a non-volatile self-sensing cell. The non-volatile self-sensing cell is connected out of the speed path of the programmable device, permitting rapid, non-volatile programming and reading operations to be conducted. According to one version, two self-sensing cells are provided with a means for selecting one of the cells for programming or read operation. Each non-volatile self-sensing cell includes a latch having cross-coupled, pull-up transistors and non-volatile pull-down cells. The cross-coupled pull-up transistors are field effect transistors having gates which are connected to the opposite sources of the cross-coupled pull-up transistors.

公开(公告)号：EP0867070A1

公开(公告)日：1998-09-30

申请号：EP97909915.0

申请日：1997-09-30

申请人： ATMEL CORPORATION

发明人： PATHAK, Jagdish ,  PAYNE, James, E. ,  PATHAK, Saroj

IPC分类号： H01L21 ,  G11C29 ,  H01L27 ,  H03K3

CPC分类号： H03K3/356008 ,  H03K3/356182

摘要： A zero power fuse circuit includes a latch means (50) having two inputs, a first input (A) being latched to ground and a second input (B) being latched to Vcc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to Vcc. A first embodiment includes two fuse element/capacitor pairs (F1, C1, F2, C2) each coupled to one of the two inputs (A, B) of the latch means. A second embodiment includes a pull-up transistor (20) and a fuse element/capacitor pair (F, C) coupled to the first and second inputs (A, B) respectively. A third embodiment includes a pull-down transistor (22) and a fuse element/capacitor pair (F, C) respectively coupled to the second and first inputs (A, B) of the latch means.

公开(公告)号：EP0740859A1

公开(公告)日：1996-11-06

申请号：EP95906819.0

申请日：1995-01-10

申请人： ATMEL CORPORATION

发明人： PAYNE, James, E. ,  PATHAK, Saroj ,  ROSENDALE, Glen, A.

IPC分类号： H01L27 ,  H01L21 ,  H02H7 ,  H02H9 ,  H03K19 ,  H04B15

CPC分类号： H03K19/00315 ,  H02H9/046

摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node (30). The first controlled path is from the signal node to (Vcc) via the source and drain electrodes of a first transistor (36). The gate of the transistor is at a soft ground by connection of the gate through a resistor (42) and an inverter (44) to a fixed voltage supply potential (Vcc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second (50) and third (52) transistors to ground. The second transistor (50) has a gate tied at (Vcc) by means of a resistor (62) and an inverter (66) to ground. The third transistor (52) is at soft ground by means of a resistor (64) and inverter (68) to (Vcc). The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor (54), if low voltage circuitry (32) is tied to the signal node (30). The fourth transistor (54) includes a gate that is tied high by connection of the gate to ground via a resistor (82) and inverter (84).

公开(公告)号：EP1547248A2

公开(公告)日：2005-06-29

申请号：EP03797833.5

申请日：2003-08-06

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  NGUYEN, Victor, V. ,  KUO, Harry, H.

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  G11C16/0433 ,  G11C16/26 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells (Fig.3). Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit (330-333), a settable latch (320-323), a signal path means (360A, 360B), and an output logic gate (350). The signal-path means coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block (402-408) for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) (700) which includes an array of word lines (pwd) and bit lines (vcol, pcol) arranged in rows and columns for addressing, an array of OR gates (740), and a plurality of output logic circuits (750).

公开(公告)号：EP0960421B1

公开(公告)日：2004-03-31

申请号：EP98903387.3

申请日：1998-01-06

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E.

IPC分类号： G11C11/419

CPC分类号： G11C11/419

摘要： An SRAM (Figs 6 and 7) monitors its WRITE/READ pin (77), and when the SRAM is in a read mode, initiates a first precharging scheme in which every complementary bitline pair (BL1, BL#1; BL2, BL#2; BL3, BL#3; BLn, BL#n) is directly coupled to Vcc via a first pmos transistor (Ld1, Ld1#; Ld2, Ld2#; Ld3, Ld#3; Ldn, Ldn#) which is permanently turned on, regardless of whether a memory cell is being read or not, and both true and false bitlines in every complementary bitline pair are coupled together via a second pmos transistor (Eq1, Eq2, Eq3, Eqn) as long as the SRAM remains in a read mode. When in a write mode, a second precharging scheme is initiated, causing the second pmos transistor to be turned off and only the first pmos transistors remain active. The termination of the write mode activates a third precharging scheme which causes all the bitlines, both true and false, within the memory array to be momentarily shorted together (S1, S2, Sn-1).

摘要翻译： SRAM（图6和图7）监视其WRITE / READ引脚（77），并且当SRAM处于读取模式时，启动第一预充电方案，其中每个互补位线对（BL1，BL＃1; BL2，BL＃ 2; BL3，BL＃3; BLn，BL＃n）通过第一pmos晶体管（Ld1，Ld1＃; Ld2，Ld2＃; Ld3，Ld＃3; Ldn，Ldn＃）直接耦合到Vcc， 不管是否正在读取存储器单元，并且只要SRAM保持在a中，每个互补位线对中的真和假位线都通过第二pmos晶体管（Eq1，Eq2，Eq3，Eqn）耦合在一起 读模式。 当处于写入模式时，启动第二预充电方案，导致第二pmos晶体管关断，并且只有第一pmos晶体管保持有效。 写入模式的终止激活第三预充电方案，其导致存储器阵列内的所有位线（真和假）一起短暂地短路（S1，S2，Sn-1）。

公开(公告)号：EP0740861B1

公开(公告)日：2003-09-24

申请号：EP95906820.6

申请日：1995-01-10

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  ROSENDALE, Glen, A.

IPC分类号： H03K17/687

CPC分类号： H03K17/693 ,  H01L2924/0002 ,  H03K17/08142 ,  H03K17/102 ,  H03K19/00315 ,  H03K19/00361 ,  H01L2924/00

摘要： A high voltage circuit includes a switching device (12) for supplying one of a high voltage (Vpp) and a low voltage (Vcc) to a controlled path including a control p-channel transistor (16) and a protection p-channel transistor (18) in series. A high voltage detector (32) is utilized to determine whether Vpp or Vcc is applied to the controlled path. The high voltage detector establishes a protecting condition for the protection p-channel transistor during Vpp operation and a non-protecting codition during Vcc operation. When the control transistor is off and the protection transistor is in a protecting condition, the voltage drop along the controlled path will cause the protection transistor to turn off, limiting the voltage across the control transistor. A second controlled path, in series with the first, includes one n-channel transistor (46) fixed at Vcc to guard against gate-aided junction breakdown in another n-channel transistor (48).

公开(公告)号：EP0740859B1

公开(公告)日：2002-06-05

申请号：EP95906819.8

申请日：1995-01-10

申请人： ATMEL CORPORATION

发明人： PAYNE, James, E. ,  PATHAK, Saroj ,  ROSENDALE, Glen, A.

IPC分类号： H03B1/04 ,  H04B1/10 ,  H04B15/00 ,  H01C7/12 ,  H03K5/00 ,  H02H1/00 ,  H02H1/04 ,  H02H3/20 ,  H02H3/22 ,  H02H7/00 ,  H02H9/04 ,  H03K19/003

CPC分类号： H03K19/00315 ,  H02H9/046

摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node (30). The first controlled path is from the signal node to (Vcc) via the source and drain electrodes of a first transistor (36). The gate of the transistor is at a soft ground by connection of the gate through a resistor (42) and an inverter (44) to a fixed voltage supply potential (Vcc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second (50) and third (52) transistors to ground. The second transistor (50) has a gate tied at (Vcc) by means of a resistor (62) and an inverter (66) to ground. The third transistor (52) is at soft ground by means of a resistor (64) and inverter (68) to (Vcc). The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor (54), if low voltage circuitry (32) is tied to the signal node (30). The fourth transistor (54) includes a gate that is tied high by connection of the gate to ground via a resistor (82) and inverter (84).

公开(公告)号：EP0914660A1

公开(公告)日：1999-05-12

申请号：EP98918655.0

申请日：1998-04-24

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PATHAK, Jagdish

IPC分类号： G11C16

CPC分类号： G11C16/22 ,  G11C16/28

摘要： A memory device includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in a erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

公开(公告)号：EP0740861A1

公开(公告)日：1996-11-06

申请号：EP95906820.0

申请日：1995-01-10

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  ROSENDALE, Glen, A.

IPC分类号： H03K17 ,  H03K19

CPC分类号： H03K17/693 ,  H01L2924/0002 ,  H03K17/08142 ,  H03K17/102 ,  H03K19/00315 ,  H03K19/00361 ,  H01L2924/00

摘要： A high voltage circuit includes a switching device (12) for supplying one of a high voltage (Vpp) and a low voltage (Vcc) to a controlled path including a control p-channel transistor (16) and a protection p-channel transistor (18) in series. A high voltage detector (32) is utilized to determine whether Vpp or Vcc is applied to the controlled path. The high voltage detector establishes a protecting condition for the protection p-channel transistor during Vpp operation and a non-protecting codition during Vcc operation. When the control transistor is off and the protection transistor is in a protecting condition, the voltage drop along the controlled path will cause the protection transistor to turn off, limiting the voltage across the control transistor. A second controlled path, in series with the first, includes one n-channel transistor (46) fixed at Vcc to guard against gate-aided junction breakdown in another n-channel transistor (48).

公开(公告)号：EP1297535B1

公开(公告)日：2007-12-26

申请号：EP01935781.3

申请日：2001-05-14

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  PATHAK, Jagdish

IPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/14

CPC分类号： G11C16/28 ,  G11C7/067 ,  G11C7/14

摘要： A reference cell (47) for use in a high speed sensing circuit includes a first sub-circuit (73) and a second sub-circuit (71). The first sub-circuit (73) has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit (71) has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistor (85, 75) having its control gate (99, 91) broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via (101, 95) is used to connect the first part to the second part.