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43 条记录 (耗时 0.014 秒)

    Minimization of engineering change pads
    14.
    发明公开
    Minimization of engineering change pads 失效
    工程改造最小化

    公开(公告)号：EP0257201A3

    公开(公告)日：1989-11-15

    申请号：EP87107230.2

    申请日：1987-05-19

    申请人： International Business Machines Corporation

    发明人： Bhatia, Harsaran Singh ,  Ecker, Mario Enrique ,  Jones, Harry Jordan ,  Malaviya, Shashi Dhar

    IPC分类号： H01L23/52 ,  G06F1/00

    CPC分类号： G06F1/22 ,  H01L23/5382 ,  H01L2924/0002 ,  Y10T307/492 ,  H01L2924/00

    摘要： A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

    Minimization of engineering change pads
    16.
    发明公开
    Minimization of engineering change pads 失效
    Minimierung von Anschlussinseln des Typs“工程变更”。

    公开(公告)号：EP0257201A2

    公开(公告)日：1988-03-02

    申请号：EP87107230.2

    申请日：1987-05-19

    申请人： International Business Machines Corporation

    发明人： Bhatia, Harsaran Singh ,  Ecker, Mario Enrique ,  Jones, Harry Jordan ,  Malaviya, Shashi Dhar

    IPC分类号： H01L23/52 ,  G06F1/00

    CPC分类号： G06F1/22 ,  H01L23/5382 ,  H01L2924/0002 ,  Y10T307/492 ,  H01L2924/00

    摘要： A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

    摘要翻译： 一种专门设计的模块和集成电路芯片，可以在芯片接收器和驱动器电路之间共享模块EC焊盘。 芯片具有其中每个接收器电路的直接正常输入线，以及来自其中每个驱动器电路的直接正常输出线以及从这些电路中的每一个到各种EC焊盘的信号线。 该芯片还包括用于在其正常和EC线路之间切换接收器电路和驱动器电路以实现电子删除功能的开关和控制电路。 在优选实施例中，大多数EC焊盘经由开关和控制电路可切换地连接到不同组的三个相邻接收器电路，驱动器电路或其组合。 该设计允许使用模块通常需要的大约一半的EC焊盘，同时允许在大多数情况下同时向三个相邻的接收器或驱动器电路进行EC连接。

    Two state memory cell
    17.
    发明公开
    Two state memory cell 失效
    与两个开关状态的存储器单元。

    公开(公告)号：EP0068164A2

    公开(公告)日：1983-01-05

    申请号：EP82104821.2

    申请日：1982-06-02

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/38

    CPC分类号： G11C11/38

    摘要： A two state memory cell includes a bipolar transistor (11) and a tunnel diode (16) shunted across the base-collector junction thereof. A constant operating current is established through the transistor (11) and the tunnel diode (16). The voltage across the tunnel diode (16) may thus be maintained at one of two stable levels, while the bipolar transistor (11) is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell.
    Since the transistor (11) is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode (16) is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced. The tunnel diode/bipolar transistor combination may be formed on a semiconductor substrate as an integrated structure, thereby providing a high density memory cell.

    Storage array having DC stable conductivity modulated storage cells
    18.
    发明公开
    Storage array having DC stable conductivity modulated storage cells 失效
    具有直流稳定电导率调制存储单元的存储阵列

    公开(公告)号：EP0043004A3

    公开(公告)日：1982-01-13

    申请号：EP81104437

    申请日：1981-06-10

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/34

    CPC分类号： G11C11/39

    摘要： The storage is fabricated in integrated circuit form, typically on a semiconductor chip, each storage cell being contained within a single isolated zone formed in the semiconductor chip. Each storage cell is DC stable and operates on a conductivity modulation principle, i.e. a cell conducts when it stores a binary "1" and the conductive state is maintained by conductivity modulation of an element of the cell, and the cell is non-conducting when storing a binary "0". In its most basic form, each cell includes at least two resistors (R2, R2'; R3, R3', R2"') formed in series in a P type semiconductor region (18, 20). At least one of the resistors, formed in a lightly doped portion of the P type region, is a variable resistor (R2, R2", R2"') having both high and low values of resistance. The high value of resistance is changed to a low value of resistance by injecting electrons from a proximate N type semiconductor region. The low value of resistance is then maintained by the current conducted through the storage cell during standby.

    3-Way exclusive or logic circuit
    19.
    发明公开
    3-Way exclusive or logic circuit 失效
    Exklusiv-Oder-Logikschaltung mit dreiEingängen。

    公开(公告)号：EP0031528A1

    公开(公告)日：1981-07-08

    申请号：EP80107859.3

    申请日：1980-12-12

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： H03K19/21 ,  H03K19/013

    CPC分类号： H03K19/013 ,  H03K19/21

    摘要： A 3-way EXCLUSIVE OR function is performed with an essentially single stage logic delay. A 3-way OR circuit (10) produces a logical "1" output whenever at least one of three input operands is " 1". A TWO AND ONLY TWO logic circuit (20A) comprising three 3-way NAND- circuits (22, 24, 26) produces a logical "0" output when two and only two of the three input operands are "1". The outputs of the OR circuit (10) and the TWO AND ONLY TWO logic circuit (20A) are DOT-ANDed at a DOT-AND circuit (30A) to provide the desired EXCLUSIVE OR function.

    摘要翻译： 执行3路EXCLUSIVE OR功能，其基本上是单级逻辑延迟。 只要三个输入操作数中的至少一个为“1”，三通OR电路（10）就产生逻辑“1”输出。 当三个输入操作数中的两个且仅两个为“1”时，包括三个三态NAND电路（22,24,26）的两个和两个双逻辑电路（20A）产生逻辑“0”输出。 OR电路（10）和两个和仅两个逻辑电路（20A）的输出在DOT-AND电路（30A）进行DOT-AND，以提供期望的EXCLUSIVE OR功能。