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36 条记录 (耗时 0.016 秒)

    Dense dynamic memory cell structure and manufacturing process
    12.
    发明公开
    Dense dynamic memory cell structure and manufacturing process 失效
    密集地可压缩动态存储单元的配置和制造过程。

    公开(公告)号：EP0070426A2

    公开(公告)日：1983-01-26

    申请号：EP82105762.7

    申请日：1982-06-29

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L27/10 ,  H01L21/82

    CPC分类号： H01L21/76202 ,  H01L23/535 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense fine connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/ sense line diffusion region.

    Verfahren zum Anbringen einer selbstausrichtenden Gateelektrode in einem V-Metalloxid-Feldeffekttransistor
    13.
    发明公开
    Verfahren zum Anbringen einer selbstausrichtenden Gateelektrode in einem V-Metalloxid-Feldeffekttransistor 失效
    在V型金属氧化物场效应晶体管附加自对准栅极电极的方法。

    公开(公告)号：EP0030640A2

    公开(公告)日：1981-06-24

    申请号：EP80107215.8

    申请日：1980-11-20

    申请人： International Business Machines Corporation

    发明人： Garnache, Richard Raymond ,  Kenney, Donald McAlpine

    IPC分类号： H01L21/28 ,  H01L21/306

    CPC分类号： H01L29/66621 ,  H01L21/30608

    摘要： Verfahren zum Herstellen von selbstausgerichteten Leitern in vertikalen, integrierten Halbleitervorrichtungen mit V-förmigen, oder rechteckigen Vertiefungen auf einer Oberfläche eines Halbleitersubstrats durch Niederschlagen einer leitenden Schicht über der Oberfläche einschließlich der Vertiefung, und Aufbringen eines eine Maske bildenden Materials über der leitenden Schicht bis eine ebene Oberfläche gebildet ist, sowie durch selektives Abätzen der Maskenschicht, bis nur noch eine Maskenschicht innerhalb der Vertiefung verbleibt und anschließend durch selektives Abätzen der danach freiliegendenTeileder leitenden Schicht.

    摘要翻译： 通过沉积在表面上的导电层，其包括凹部产生在与半导体基板的表面上的V形，或矩形的孔垂直集成的半导体器件自吸面向导体，并施加一个掩模形成材料的导电层上的电平的方法 表面被选择性地蚀刻导电层的随后暴露部分形成并通过选择性地蚀刻掩模层保留，直到凹部内仅一个掩模层，然后。

    A semiconductor trench capacitor structure
    16.
    发明公开
    A semiconductor trench capacitor structure 失效
    半导体电容电容器结构

    公开(公告)号：EP0265616A3

    公开(公告)日：1989-08-30

    申请号：EP87111966.5

    申请日：1987-08-18

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L29/94 ,  H01L27/10

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L29/945

    摘要： A semiconductor trench capacitor structure (240) having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer (340, 360) formed along the upper portion of the trench side walls. The trench isolation structure facilitates the construction of trench capaci­tors of greater storage capacity in a given space and allows the capacitors to abut adjacent capacitors and other devices.

    Dynamic RAM cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
    17.
    发明公开
    Dynamic RAM cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes 失效
    具有具有共同严重存储电容器，其通过桥接触和栅电极的侧壁定义的动态RAM单元。

    公开(公告)号：EP0264858A2

    公开(公告)日：1988-04-27

    申请号：EP87115186.6

    申请日：1987-10-16

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L27/10 ,  H01L21/82

    CPC分类号： H01L27/10861 ,  H01L21/28525 ,  H01L27/10829 ,  Y10S257/90

    摘要： A one-device shared trench memory cell, in which the polysilicon (22,24) and dielectric layers (26,26A) within the trench (20) extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder (36). The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide a bridge contact (30) that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode (34) to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

    摘要翻译： 一个一设备共享沟槽的存储单元，其中，所述沟槽（20）内的多晶硅（22,24）和电介质层（26,26A）延伸的沟槽的表面的上方以形成心轴结构。 多晶硅层共形沉积在该心轴结构。 掺杂剂离子从沟槽到所述保形多晶硅层内的掺杂多晶硅扩散，并从保形多晶硅层到设置其下（36）在基板的一部分上。 在溶剂中做优先攻击未掺杂的多晶硅，以提供一个接触桥（30）做了保形多晶硅进行蚀刻自对准于所述沟槽内，并扩散区域的多晶硅。 FET的多个形成在所述沟槽的任一侧上，通过使用一个侧壁限定的栅极电极（34）的最大化密度。 细胞产生，“聚对多晶硅”和“多晶材料 - 衬底”存储电容器组合没有最大程度地增强电荷存储能力。

    Memory array
    18.
    发明公开
    Memory array 失效
    内存阵列

    公开(公告)号：EP0186745A3

    公开(公告)日：1988-02-10

    申请号：EP85113178

    申请日：1985-10-17

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4074 ,  G11C11/404

    摘要： A memory array is provided which includes a common sense line (SL) to which is connected first and second series of cells, each cell of each series includes a storage capacitor (C), switching means (T) and a bit line (BL) connected to a plate of the storage capacitor (C), with a common word line (WL) connected to the control electrodes of each of the switching means. The switching means, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.

    High density memory
    19.
    发明公开
    High density memory 失效
    高密度的回忆。

    公开(公告)号：EP0221380A2

    公开(公告)日：1987-05-13

    申请号：EP86113867.5

    申请日：1986-10-07

    申请人： International Business Machines Corporation

    发明人： Kenney, Donald McAlpine

    IPC分类号： H01L27/10

    CPC分类号： H01L27/10864 ,  H01L21/762 ,  H01L27/10841

    摘要： A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.