公开(公告)号：EP3336561A1

公开(公告)日：2018-06-20

申请号：EP16203729.5

申请日：2016-12-13

Applicant: NXP B.V.

Inventor： LIN, Yu ,  JANSSEN, Erwin ,  DORIS, Konstantinos ,  DYACHENKO, Vladislav ,  ZANIKOPOULOS, Athon

IPC: G01R23/00 ,  G06F1/02 ,  H03D7/00

CPC classification number: G01S13/341 ,  G01R23/00 ,  G01R23/04 ,  G01S13/342 ,  G06F1/022 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03J3/04

Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component

公开(公告)号：EP2229736B1

公开(公告)日：2015-07-29

申请号：EP08853646.1

申请日：2008-11-24

Applicant: NXP B.V.

Inventor： BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/12 ,  H04B1/18 ,  H04N5/775

CPC classification number: H04B1/12 ,  H04B1/18

公开(公告)号：EP2351232A1

公开(公告)日：2011-08-03

申请号：EP09760000.1

申请日：2009-11-12

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/00 ,  H03H17/02 ,  H04N5/44

CPC classification number: H04B1/001 ,  H03H17/06 ,  H03H2218/08 ,  H04B1/0025

Abstract: A multi-channel receiver comprising an ADC and a multi-band, multi-channel selector. The ADC converts a broad-band multi-channel signal into a digital signal. The digital signal is then broken into sub-bands each containing a plurality of channels. A channel selector selects desired channels from the appropriate sub-band. The multi-channel receiver may deliver simultaneous channels equal to the number of channel selectors that have been implemented. The multi-channel receiver may be implemented on a single integrated circuit.

公开(公告)号：EP2229736A1

公开(公告)日：2010-09-22

申请号：EP08853646.1

申请日：2008-11-24

Applicant: NXP B.V.

Inventor： BREKELMANS, Johannes, H., A. ,  DORIS, Konstantinos ,  JANSSEN, Erwin

IPC: H04B1/12 ,  H04B1/18 ,  H04N5/775

CPC classification number: H04B1/12 ,  H04B1/18

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog- digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

公开(公告)号：EP2156562A2

公开(公告)日：2010-02-24

申请号：EP08763118.0

申请日：2008-05-27

Applicant: NXP B.V.

Inventor： DORIS, Konstantinos

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/0678 ,  H03M1/066 ,  H03M1/1215

Abstract: The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input -signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor.