公开(公告)号：EP1716491B1

公开(公告)日：2009-12-16

申请号：EP04754870.6

申请日：2004-06-10

申请人： Silicon Image, Inc.

发明人： KIM, Ook ,  LEE, Eric ,  KIM, Gyudong ,  JANG, Zeehoon ,  SUNG, Baegin ,  KIM, Nam, Hoon ,  AHN, Gijung ,  HWANG, Seung, Ho

IPC分类号： G06F13/38

CPC分类号： G06F13/385

公开(公告)号：EP2947809A1

公开(公告)日：2015-11-25

申请号：EP15177026.0

申请日：2007-10-31

申请人： Silicon Image, Inc.

发明人： SHIM, Daeyun ,  KIM, Min-Kyu ,  KIM, Gyudong ,  JUNG, Keewook ,  HWANG, Seung Ho

IPC分类号： H04L5/20

CPC分类号： H04L5/20

摘要： The present disclosure relates to a chip comprising transmitters configured to transmit differential signals on conductors, wherein the conductors include first and second pairs of conductors, and the differential signals include first differential signals to be transmitted to the first pair of conductors and second differential signals to be transmitted to the second pair of conductors. The chip furhter comprises a current mode circuitry configured to selectively modulate a common mode voltage of the differential signals to communicate data and and a common mode detection circuitry configured to detect changes in the common mode voltage. Furthermore, the present disclosure relates to a second chip including receivers configured to receive differential signals on conductors, wherein the conductors include first and second pairs of conductors, and the differential signals include first differential signals to be received by the first pair of conductors and second differential signals to be received by the second pair of conductors. The second chip further comprises a current mode circuitry configured to selectively modulate a common mode voltage of the differential signals to communicate data and a common mode detection circuitry configured to detect changes in the common mode voltage.

摘要翻译： 本公开涉及一种包括发射机的芯片，该发射机被配置为在导体上传输差分信号，其中导体包括第一和第二对导体，并且差分信号包括要传输到第一对导体的第一差分信号和第二差分信号， 被传输到第二对导体。 芯片形成器包括被配置为选择性地调制差分信号的共模电压以传送数据的电流模式电路，以及被配置为检测共模电压的变化的共模检测电路。 此外，本公开涉及包括被配置为在导体上接收差分信号的接收器的第二芯片，其中所述导体包括第一和第二对导体，并且所述差分信号包括要由第一对导体接收的第一差分信号和第二对导体 差分信号由第二对导体接收。 第二芯片还包括被配置为选择性地调制差分信号的共模电压以传送数据的电流模式电路，以及被配置为检测共模电压的变化的共模检测电路。

公开(公告)号：EP2351141A2

公开(公告)日：2011-08-03

申请号：EP09749258.1

申请日：2009-10-27

申请人： Silicon Image, Inc.

发明人： JONES, Graeme, Peter ,  SHIM, Daeyun ,  RANADE, Shrikant ,  KIM, Gyudong ,  KIM, Ook

IPC分类号： H01P1/10

CPC分类号： G09G5/006 ,  G06F13/409 ,  G09G2370/10 ,  G09G2370/12 ,  H04L12/40006

摘要： Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.

公开(公告)号：EP2272251A1

公开(公告)日：2011-01-12

申请号：EP09714761.5

申请日：2009-02-26

申请人： Silicon Image, Inc.

发明人： CHOI, Hoon ,  KIM, Gyudong ,  KIM, Ook ,  LYLE, James, D. ,  PEYSAKHOVICH, Alexander ,  SCHUMACHER, Michael ,  SHIM, Daeyun

IPC分类号： H04N5/44

CPC分类号： H04L63/0876 ,  G09G5/006 ,  G09G2370/12 ,  G11B20/00086 ,  G11B20/00463 ,  H04N5/4401 ,  H04N5/913 ,  H04N7/1675 ,  H04N21/2541 ,  H04N21/4122 ,  H04N21/4367 ,  H04N21/4408 ,  H04N21/835

摘要： A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.

摘要翻译： 公开了一种用于预先认证端口的方法，装置和系统。 在一个实施例中，识别在发送设备和接收设备之间促成媒体内容的通信的活动端口，而活动端口与第一高清内容保护（HDCP）引擎相关联。 然后，标识处于空闲模式的非活动端口作为活动端口的备用端口，而非活动端口与第二个HDCP引擎相关联。 对每个非活动端口执行预认证，以便预先认证的非活动端口随后可以在执行端口切换时替换活动端口。

公开(公告)号：EP0968580B1

公开(公告)日：2006-06-21

申请号：EP99916105.2

申请日：1999-01-20

申请人： Silicon Image, Inc.

发明人： MOON, Yongsam ,  JEONG, Deog-Kyoon ,  KIM, Gyudong

IPC分类号： H04B15/04 ,  H04B1/707

CPC分类号： H04B1/707 ,  G06F1/04 ,  H04B15/00 ,  H04B15/04 ,  H04B2215/064

摘要： A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

公开(公告)号：EP3306851A1

公开(公告)日：2018-04-11

申请号：EP17200793.2

申请日：2007-10-31

申请人： Silicon Image, Inc.

发明人： SHIM, Daeyun ,  KIM, Min-Kyu ,  KIM, Gyudong ,  JUNG, Keewook ,  HWANG, Seung Ho

IPC分类号： H04L5/20

CPC分类号： H04L5/20

摘要： A system comprising a transmitter chip and a receiver chip is disclosed. The transmitter chip comprises a first transmitter circuit configured to transmit a first differential signal on a first pair of conductors and common mode detection circuitry configured to detect changes in a first common mode voltage of the first pair of conductors to obtain a first common mode data signal. The receiver chip comprises a first receiver circuit configured to receive the first differential signal from the first pair of conductors and current mode circuitry configured to modulate the first common mode voltage of the first pair of conductors to communicate the first common mode data signal to the transmitter chip.

摘要翻译： 公开了一种包括发射器芯片和接收器芯片的系统。 发送器芯片包括被配置为在第一对导体上发送第一差分信号的第一发送器电路以及被配置为检测第一对导体的第一共模电压的变化以获得第一共模数据信号的共模检测电路 。 接收器芯片包括被配置为从第一对导体接收第一差分信号的第一接收器电路以及被配置为调制第一对导体的第一共模电压以将第一共模数据信号传送到发射器的电流模式电路 芯片。

公开(公告)号：EP2664097A2

公开(公告)日：2013-11-20

申请号：EP12734442.2

申请日：2012-01-11

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  CHOI, Hoon ,  WILCOX, Richard, J. ,  HARRELL, Chandlee

IPC分类号： H04L7/02 ,  H04L12/56 ,  H04N21/242

CPC分类号： H04N7/0352 ,  G09G5/008 ,  G09G2370/04 ,  G09G2370/10 ,  H04N21/4305

摘要： A mechanism for facilitating clock recovery for streaming content over a packetized network is described. A method of embodiments includes receiving an estimated data stream at a first device. The estimated data stream may include estimated data format information relating to a data stream expected to be received at the first device. The method may further include performing, at the first device, clock regeneration of the estimated data stream based on the estimated data format information. The clock regeneration may include performing clock recovery of the estimated data stream.

公开(公告)号：EP2238531A1

公开(公告)日：2010-10-13

申请号：EP08870128.9

申请日：2008-12-02

申请人： Silicon Image, Inc.

发明人： KIM, Gyudong ,  SUNG, Baegin ,  CHOI, Hoon

IPC分类号： G06F3/14 ,  G09G5/00 ,  G06F13/40 ,  H04L29/06 ,  H04N7/10 ,  H04M1/725

CPC分类号： G06F3/14 ,  G06F13/4072 ,  G09G5/006 ,  G09G2370/045 ,  G09G2370/047 ,  H04L65/605

摘要： A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled with the transmitter, the receiver configured to receive the single channel, and to unmerge the single channel into the multiple channels.

公开(公告)号：EP1733474A2

公开(公告)日：2006-12-20

申请号：EP04755055.3

申请日：2004-06-10

申请人： Silicon Image, Inc.

发明人： KIM, Ook ,  KIM, Gyudong

IPC分类号： H03H7/30

CPC分类号： H04L25/03019

摘要： In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (40-43) (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry (54) for generating an equalization control signal (CTL) for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.

公开(公告)号：EP1050138B1

公开(公告)日：2006-03-15

申请号：EP99905447.1

申请日：1999-01-20

申请人： Silicon Image, Inc.

发明人： AHN, Gijung ,  JEONG, Deog-Kyoon ,  KIM, Gyudong

IPC分类号： H04L25/02

CPC分类号： H04L25/028 ,  H04L7/0337 ,  H04L25/0278 ,  H04L25/0292

摘要： New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continuously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.