公开(公告)号：EP0405174A2

公开(公告)日：1991-01-02

申请号：EP90110384.6

申请日：1990-05-31

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Takatori, Sunao ,  Kumagai, Ryohei ,  Yamamoto, Makoto ,  Matsumoto, Koji

IPC分类号： G06F15/80

CPC分类号： G06N3/08

摘要： An adaptation method for a data processing system comprising a plurality of neurons each of which outputs an output according to a comparison between a sum of multiplied inputs by weights and a threshold, characterized in the following steps:
The threshold of the neuron which has generated significant output at certain point of time is compulsorily increased to a maximal value;
The weight of the neuron is adapted for a constant value of the inputs; and the threshold is decreased to a value at the point.

摘要翻译： 一种用于数据处理系统的适应方法，包括多个神经元，每个神经元根据权重和相乘输入之和之间的比较来输出输出，其特征在于以下步骤：产生显着的神经元的阈值 在某个时间点的输出强制增加到最大值; 神经元的权重适用于输入的恒定值; 并且阈值减小到该点处的值。

公开(公告)号：EP0855796A3

公开(公告)日：2002-07-31

申请号：EP98101319.6

申请日：1998-01-26

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Zhou, Changming ,  Yamamoto, Makoto ,  Zhou, Xuping ,  Takatori, Sunao ,  Qin, Xiaoling

IPC分类号： H03H17/02

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： The invention provides according to a first aspect a low electric power consumption matched filter. The signal received at an input terminal is input to a shift-register having stages equal to the spread code length number after conversion into M-bit digital signals in an analog-to-digital converter. The outputs of the shift-register stages are input to EXCLUSIVE-OR circuits set corresponding to each stage, so that EXCLUSIVE-OR is performed between the outputs and corresponding spread code bits d 1 to d N . The outputs of the EXCLUSIVE-OR circuits are analogously added in an analog adder and output from an output terminal. According to a second aspect the invention provides a filter circuit using an analog operation circuit to prevent lowering of operation accuracy caused by the residual charge. Input analog signals successively undergo sampling and holding in each sampling and holding circuit, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sampling and holding circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sampling and holding circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is set double and refreshed in the same way.

公开(公告)号：EP1069732A2

公开(公告)日：2001-01-17

申请号：EP00115154.7

申请日：2000-07-12

申请人： Yozan Inc.

发明人： Takatori, Sunao, c/o Yozan Inc. ,  Yamamoto, Makoto

IPC分类号： H04L12/40 ,  H04Q9/00

CPC分类号： H04L29/12254 ,  H04B3/542 ,  H04B2203/5445 ,  H04L12/28 ,  H04L29/12839 ,  H04L61/2038 ,  H04L61/6022 ,  H04Q9/14

摘要： Power supply sockets of a distributing system of interior power supply wiring are provided with a communication distributing terminal, and apparatus (A1-An) are provided with a terminal unit 2 for connection to a communication line CL. A unique address is assigned for the terminal unit 2. A communication line CL is provided with a timing clock supply line TL, a unique address communication line AL, and a local area network (LAN) line LL, thereby connecting the apparatus (A1-An) connected to the power supply socket to the communication line CL. The unique address of the terminal unit 2 connected to the communication line CL is transmitted to the unique address communication line AL, and communication with the terminal unit 2 is controlled through the LAN line LL by the communication control unit 1. The terminal unit 2 transmits its own unique address to the unique address transmission line AL during a predetermined address registration period, when it failed to find its own unique address in unique addresses transmitted from the communication control unit 1. Thereby realizes very easy communication between the apparatus (A1-An).

摘要翻译： 内部电源配线分配系统的电源插座设置有通信分配终端，设备（A1-An）设置有用于连接到通信线路CL的终端单元2。 为终端单元2分配唯一的地址。通信线路CL设置有定时时钟供给线TL，唯一地址通信线路AL和局域网（LAN）线路LL，从而将设备（A1- A）将电源插座连接到通信线路CL。 连接到通信线路CL的终端单元2的唯一地址被发送到唯一地址通信线路AL，并且通过通信控制单元1通过LAN线路LL来控制与终端单元2的通信。终端单元2发送 当在通信控制单元1发送的唯一地址中找不到其自己的唯一地址时，在预定的地址注册期间，它自己的唯一地址到唯一的地址传输线AL。从而实现设备（A1-An ）。

公开(公告)号：EP0707274B1

公开(公告)日：2000-05-03

申请号：EP95114823.8

申请日：1995-09-20

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： G06J1/00

CPC分类号： G06J1/00

公开(公告)号：EP0855796A2

公开(公告)日：1998-07-29

申请号：EP98101319.6

申请日：1998-01-26

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Zhou, Changming ,  Yamamoto, Makoto ,  Zhou, Xuping ,  Takatori, Sunao ,  Qin, Xiaoling

IPC分类号： H03H17/02

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： The invention provides according to a first aspect a low electric power consumption matched filter. The signal received at an input terminal is input to a shift-register having stages equal to the spread code length number after conversion into M-bit digital signals in an analog-to-digital converter. The outputs of the shift-register stages are input to EXCLUSIVE-OR circuits set corresponding to each stage, so that EXCLUSIVE-OR is performed between the outputs and corresponding spread code bits d 1 to d N . The outputs of the EXCLUSIVE-OR circuits are analogously added in an analog adder and output from an output terminal. According to a second aspect the invention provides a filter circuit using an analog operation circuit to prevent lowering of operation accuracy caused by the residual charge. Input analog signals successively undergo sampling and holding in each sampling and holding circuit, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sampling and holding circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sampling and holding circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is set double and refreshed in the same way.

摘要翻译： 本发明根据第一方面提供一种低功耗匹配滤波器。 在模数转换器中转换成M位数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级设置的EXCLUSIVE-OR电路，从而在输出和对应的扩展码位d1至dN之间执行EXCLUSIVE-OR。 EXCLUSIVE-OR电路的输出类似地添加到模拟加法器中并从输出端子输出。 根据第二方面，本发明提供一种使用模拟运算电路的滤波电路，以防止由剩余电荷引起的操作精度降低。 输入模拟信号在每个采样和保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并在加法电路中相加。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样和保持电路和乘法电路由模拟运算电路形成，并且每个包括用于消除剩余电荷的开关。 正常工作的采样和保持电路和乘法电路通过提供更换其功能的电路来顺序刷新。 加法电路设置为双倍并以相同的方式刷新。

公开(公告)号：EP0841701A1

公开(公告)日：1998-05-13

申请号：EP97119272.9

申请日：1997-11-04

申请人： YOZAN INC.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Yamamoto, Makoto

IPC分类号： H01L27/08 ,  G01R31/316

CPC分类号： H01L22/34 ,  H01L27/08 ,  H01L2924/3011

摘要： The present invention provides a circuit enable to measure the component characteristics deviation of an integrated semiconductor circuit system. It has the structure that an input impedance and a feedback impedance are connected to an inverting amplifying circuit consisting of an odd number of stages of inverters. Enough impedance units are connected to make one of them the reference impedance and another the measurement object, known voltage is input to the inverting amplifying circuit, and its output is measured from the outside of the integrated semiconductor circuit system.

摘要翻译： 本发明提供一种能够测量集成半导体电路系统的元件特性偏差的电路。 它具有输入阻抗和反馈阻抗连接到由奇数级反相器组成的反相放大电路的结构。 连接足够的阻抗单元使其中的一个成为参考阻抗，另一个是测量对象，已知电压被输入到反相放大电路，其输出从集成半导体电路系统的外部测量。

公开(公告)号：EP0757450A2

公开(公告)日：1997-02-05

申请号：EP96112313.0

申请日：1996-07-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

公开(公告)号：EP0756239A1

公开(公告)日：1997-01-29

申请号：EP96111793.4

申请日：1996-07-22

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Zhou, Changming ,  Motohashi, Kazunori ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： G06G7/14 ,  H03M1/80 ,  G06J1/00

CPC分类号： G06J1/00 ,  G06G7/14

摘要： The present invention provides a weighted addition circuit for realizing the function of sampling and holding and weighted addition by a smaller circuit than a conventional one. In the weighted addition circuit according to the present invention, a capacitive coupling is connected to a plurality of switches connected only to an input voltage, and a voltage is held and a weight is added in the capacitive coupling.

摘要翻译： 本发明提供了一种加权加法电路，用于通过比常规电路更小的电路来实现采样和保持加权相加的功能。 在根据本发明的加权加法电路中，电容耦合连接到仅连接到输入电压的多个开关，并且保持电压并且在电容耦合中增加权重。

公开(公告)号：EP0586914B1

公开(公告)日：1997-01-02

申请号：EP93112888.8

申请日：1993-08-11

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： H04N7/24

CPC分类号： H04N19/63

公开(公告)号：EP0736976A1

公开(公告)日：1996-10-09

申请号：EP95105306.5

申请日：1995-04-07

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： H03K19/0948 ,  H03K19/003

CPC分类号： H03K19/00384

摘要： This invention have an object to provide an inverter circuit to realize the stable efficient without the influence of the dispersion of characteristics value of each inverter, constructed by connecting a plural number of inverters INV1, INV2, ..., INVn in parallel between input terminal VIN and output terminal VOUT.

摘要翻译： 本发明的目的是提供一种逆变器电路，其不受每个逆变器的特性值的偏差的影响而实现稳定的效率，其通过在输入端子之间并联连接多个反相器INV1，INV2，...，INVn而构成 VIN和输出端子VOUT。