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223 条记录 (耗时 0.019 秒)

    MEMORY DEVICE WITH A DATA HOLD LATCH
    11.
    发明公开
    MEMORY DEVICE WITH A DATA HOLD LATCH 审中-公开
    具有数据保持触发器存储设备

    公开(公告)号：EP1915502A2

    公开(公告)日：2008-04-30

    申请号：EP05744165.1

    申请日：2005-05-05

    申请人： Freescale Semiconductor, Inc.

    发明人： The designation of the inventor has not yet been filed

    IPC分类号： E06C7/10

    CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/16

    摘要： A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

    Clock recovery circuit and data receiving circuit
    14.
    发明公开
    Clock recovery circuit and data receiving circuit 有权
    时钟恢复电路和数据接收电路

    公开(公告)号：EP1355444A3

    公开(公告)日：2005-05-11

    申请号：EP03252155.1

    申请日：2003-04-04

    申请人： FUJITSU LIMITED

    发明人： Yamaguchi, Hisakatsu, c/o Fujitsu Limited ,  Tamura, Hirotaka, c/o Fujitsu Limited

    IPC分类号： H04L7/033

    CPC分类号： H03L7/091 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  H04L7/0331

    摘要： A clock recovery circuit has a boundary detection circuit (20, 21, 22, 23) detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit (42) and a variation reducing circuit (9). The boundary detection timing varying circuit (42) dynamically varies boundary detection timing in the boundary detection circuit (20, 21, 22, 23) by applying a variation to the first signal, and the variation reducing circuit (9) reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit (42).

    TIMING CONTROL MEANS FOR AUTOMATIC COMPENSATION OF TIMING UNCERTAINTIES
    17.
    发明公开
    TIMING CONTROL MEANS FOR AUTOMATIC COMPENSATION OF TIMING UNCERTAINTIES 审中-公开
    设备用于控制同步进行同步的不确定性自动平衡

    公开(公告)号：EP1360569A2

    公开(公告)日：2003-11-12

    申请号：EP01941340.0

    申请日：2001-05-22

    申请人： Acuid Corporation Limited

    发明人： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger

    IPC分类号： G06F1/04 ,  H03L7/081 ,  H04L7/02 ,  G11C7/10

    CPC分类号： H04L7/02 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L25/14

    摘要： The present invention relates to the reducing timing uncertainties in high-performance digital circuitry and more specifically, to a timing control means and a method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal. The invention is preferably implemented in a self calibrated receiver and a self calibrating transmitter. Also, the invention can be employed in a digital interface between two items or within a circuit where there is a requirement for tight timing control such as requirement for a low skew between the channels of a register.

    Dynamic-latch-receiver with self-reset pointer
    19.
    发明公开
    Dynamic-latch-receiver with self-reset pointer 审中-公开
    动态接收机锁存器电路与具有自动复位的指针

    公开(公告)号：EP1041571A3

    公开(公告)日：2001-02-28

    申请号：EP00103968.4

    申请日：2000-02-25

    申请人： International Business Machines Corporation ,  Infineon Technologies AG

    发明人： Kirihata, Toshiaka ,  Mueller, Gerhard ,  Hanson, David R.

    IPC分类号： G11C7/10 ,  H03K3/356

    CPC分类号： G11C7/1087 ,  G11C7/1078

    摘要： A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.