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    Vault shaped target and high-field magnetron
    11.
    发明公开
    Vault shaped target and high-field magnetron 审中-公开
    GewölbtesTarget和Magnetron mit starkem Feld

    公开(公告)号：EP1119017A2

    公开(公告)日：2001-07-25

    申请号：EP01300337.1

    申请日：2001-01-16

    申请人： APPLIED MATERIALS, INC.

    发明人： Gopalraja, Parburam ,  Fu, Jianming ,  Chen, Fusen ,  Dixit, Girish ,  Xu, Zheng ,  Athreya, Sankaram ,  Wang, Wei D. ,  Sinha, Ashok K.

    IPC分类号： H01J37/34

    CPC分类号： H01L21/76844 ,  C23C14/046 ,  C23C14/165 ,  C23C14/185 ,  C23C14/225 ,  C23C14/35 ,  H01J37/3405 ,  H01J37/342 ,  H01J37/3423 ,  H01J37/3452 ,  H01J37/3455 ,  H01J37/3458 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2221/1089

    摘要： The disclosure relates to a target and magnetron for a plasma sputter reactor (10). The target (12) has an annular vault (18) facing the wafer (20) to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. Preferably, the magnetron (14) includes annular magnets (32) of opposed polarities disposed behind the two vault sidewalls (22, 24) and a small closed unbalanced magnetron of nested magnets (30) of opposed polarities scanned along the vault roof. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.

    摘要翻译： 本公开涉及用于等离子体溅射反应器（10）的靶和磁控管。 目标（12）具有面向要被溅射涂覆的晶片（20）的环形拱顶（18）。 位于拱顶周围的各种类型的磁性装置产生一个支撑等离子体的磁场，该等离子体延伸在大容积的拱顶上。 优选地，磁控管（14）包括设置在两个拱顶侧壁（22,24）后面的相对极性的环形磁体（32）和沿着拱顶顶部扫描的具有相对极性的嵌套磁体（30）的小闭合不平衡磁控管。 与本发明的反应器或其他反应器的集成铜通孔填充方法包括铜的高度离子化溅射沉积的第一步骤，其可任选地用于去除通孔底部的阻挡层，第二步更中性，更低 能够充分地溅射沉积铜以完成种子层，以及将铜电镀到孔中以完成金属化的第三步骤。 前两个步骤也可以与阻隔金属一起使用。

    A method to avoid copper contamination on the sidewall of a via or a dual damascene structure
    12.
    发明公开
    A method to avoid copper contamination on the sidewall of a via or a dual damascene structure 有权
    用于防止接触孔的侧表面或双镶嵌结构的铜污染方法

    公开(公告)号：EP1102315A2

    公开(公告)日：2001-05-23

    申请号：EP00640011.3

    申请日：2000-11-13

    申请人： Chartered Semiconductor Manufacturing Pte Ltd.

    发明人： Gupta, Subhash ,  Ho, Kwok Keung Paul ,  Shou, Mei-Sheng ,  Chooi, Simon

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76877

    摘要： A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

    摘要翻译： 一种新的方法，以防止在通过或通过形成在所述第一铜金属化的封端层的双镶嵌蚀刻中描述的金属间介电层的铜污染。 第一铜金属化是形成在电介质层，覆盖在半导体衬底worin阻挡金属层被形成下层的第一铜金属化和覆盖所述介电层。 第一铜金属化被平坦化，然后蚀刻以形成电介质层的表面之下的凹槽。 导电覆盖层沉积覆在凹部内的第一铜金属化和覆盖所述介电层。 除了使用以上的几种方法之一的凹部内的第一铜金属化导电覆盖层被去除。 的金属间介电层被沉积覆盖在介电层和所述覆盖层覆盖所述第一导电铜金属化。 通孔或双镶嵌开口，通过所述金属间介电层以覆盖层导电worin的导电覆盖层蚀刻防止蚀刻过程中，金属间介电层的铜污染。 通孔或双镶嵌开口内填充有金属层以完成集成电路器件的制造电连接。

    Semiconductor connection structure and method
    13.
    发明公开
    Semiconductor connection structure and method 失效
    Halbleiterverbindungsstruktur und Verfahren

    公开(公告)号：EP1098366A1

    公开(公告)日：2001-05-09

    申请号：EP01100643.4

    申请日：1995-12-05

    申请人： STMicroelectronics, Inc.

    发明人： Miller, Robert O. ,  Smith, Gregory C.

    IPC分类号： H01L23/522 ,  H01L23/532

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.

    摘要翻译： 提供一种电连接结构，用于在覆盖钨插入连接结构的铝互连层的形成期间保护接触开口内的阻挡金属层。 覆盖阻挡金属层的沉积钨丝塞被充分回蚀，以在开口处产生轻微的凹陷。 然后选择性地沉积薄层的钨以填充凹部。 在铝互连层形成期间，该层用作蚀刻停止层并保护下面的阻挡金属层。

    Process to improve filling of contact holes by electroplating
    14.
    发明公开
    Process to improve filling of contact holes by electroplating 审中-公开
    通过电镀改善接触孔填充的工艺

    公开(公告)号：EP1081753A2

    公开(公告)日：2001-03-07

    申请号：EP00307411.9

    申请日：2000-08-29

    申请人： Applied Materials, Inc.

    发明人： Chen, Fusen ,  Xu, Zheng ,  Ding, Peijun ,  Chin, Barry ,  Sinha, Ashok

    IPC分类号： H01L21/288

    CPC分类号： H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877

    摘要： The disclosure relates to a method for filling a structure on a substrate (50) comprising: depositing a barrier layer (52) on one or more surfaces of the structure, depositing a seed layer (58) over the barrier layer, removing a portion of the seed layer, and electrochemically depositing a metal (78) to fill the structure. Preferably, a portion of all of the seed layer formed on the sidewall portion of the structure is removed using an electrochemical de-plating process prior to the electroplating process.

    摘要翻译： 本公开涉及一种用于在基底（50）上填充结构的方法，包括：在结构的一个或多个表面上沉积阻挡层（52），在阻挡层上沉积种子层（58），去除 种子层，并电化学沉积金属（78）以填充结构。 优选地，在电镀工艺之前，使用电化学去电镀工艺去除在结构的侧壁部分上形成的全部种子层的一部分。

    Semiconductor device including a wiring layer
    15.
    发明公开
    Semiconductor device including a wiring layer 失效
    半导体器件，包括布线层

    公开(公告)号：EP0552968A3

    公开(公告)日：1993-09-29

    申请号：EP93300459.0

    申请日：1993-01-22

    申请人： SAMSUNG ELECTRONICS CO. LTD.

    发明人： Lee, Sang-In ,  Park, Chang-Soo

    IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L21/90

    CPC分类号： H01L21/76865 ,  H01L21/3105 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device comprising a wiring layer having a novel contact structure. The semiconductor device includes a semiconductor substrate (31, 51), an insulating layer having an opening (contact hole via a recess), a reactive spacer (37a) formed on the sidewall of the opening or a reactive layer (57a) formed on the sidewall and on the bottom surface of the opening and a conductive layer (39a, 59a) formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer (37a, 57a) is formed on the sidewall of the opening, when the conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer (37a, 57a) improves the reflow of the conductive layer (39, 59) during a heat-treating step for filling the opening at a high temperature below a melting temperature. This, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 µm in size and having an aspect ratio greater than 1.0, can be completely filled with Al, to thereby enhance the reliability of the wiring of a semiconductor device.