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23 条记录 (耗时 0.008 秒)

    PHASE-LOCKED LOOP BASED CONTROLLER FOR ADJUSTING AN ADAPTIVE CONTINUOUS-TIME FILTER
    11.
    发明公开
    PHASE-LOCKED LOOP BASED CONTROLLER FOR ADJUSTING AN ADAPTIVE CONTINUOUS-TIME FILTER 有权
    在PHASENEINRASTKREIS基于控制装置设定一个自适应时间连续滤波器

    公开(公告)号：EP2137827A2

    公开(公告)日：2009-12-30

    申请号：EP08826066.6

    申请日：2008-04-18

    申请人： Skyworks Solutions, Inc.

    发明人： YOUSSOUFIAN, Edward ,  YATES, David ,  ISMAIL, Aly, M. ,  HATCHER, Geoffrey

    IPC分类号： H04B1/16

    CPC分类号： H03H21/0012 ,  H03H11/1291 ,  H03H2210/021 ,  H03H2210/043 ,  H03J2200/10

    摘要： A direct conversion radio-frequency (RF) receiver includes a controller and an adaptive continuous-time filter. The adaptive continuous-time filter receives a multiple-bit control signal generated by the controller to adjust a characteristic of the continuous-time filter. The controller generates the multiple-bit control signal in response to process variation in the semiconductor material used to implement the controller and the adaptive continuous-time filter. A method for tuning an adaptive continuous-time filter comprises determining a RC time constant, converting the RC time constant to a digital word, comparing a select bit of the digital word to a respective bit of a predetermined reference word to generate a control bit, applying the control bit to an adjustable element to modify the RC time constant, repeating the determining, converting, comparing and applying steps until the control bits generate an output word and providing the output word to the adaptive continuous-time filter.

    TRANSDUCER ASSEMBLY WITH MODIFIABLE BUFFER CIRCUIT AND METHOD FOR ADJUSTING THEREOF
    12.
    发明公开
    TRANSDUCER ASSEMBLY WITH MODIFIABLE BUFFER CIRCUIT AND METHOD FOR ADJUSTING THEREOF 审中-公开
    具有可调缓冲电路转换器装置和表决程序

    公开(公告)号：EP1602260A2

    公开(公告)日：2005-12-07

    申请号：EP04719182.0

    申请日：2004-03-10

    申请人： KNOWLES ELECTRONICS, INC.

    发明人： BOOR, Steven, E.

    IPC分类号： H04R3/00

    CPC分类号： H04R29/006 ,  H03F3/505 ,  H03F13/00 ,  H03F21/00 ,  H03H7/25 ,  H03H2210/043 ,  H04R1/04 ,  H04R3/04 ,  H04R25/00 ,  H04R25/407

    摘要： A method and system for adjusting the frequency response characteristics of a transducer assembly (312) is disclosed. The transducer assembly (312) includes a modifiable buffer circuit (100) being generally enclosed within a housing (314). Electrical signal connections for modifying the operating state of the modifiable buffer circuit (100) are accessible outside the housing (314). The modifiable buffer circuit (100) further includes a plurality of signal inputs (234) and outputs (230), the plurality of signal inputs (234) are accessible from outside the housing. A predetermined relationship exists between the plurality of signal inputs (234) and the plurality of outputs (230). A resistor network (224) is operably connected to the plurality of outputs (230) wherein a portion of the resistor network (224) is operably disconnected from a filter network (218) in response to the plurality of signal inputs (234).

    METHOD AND APPARATUS FOR TUNING RESISTORS AND CAPACITORS
    15.
    发明公开
    METHOD AND APPARATUS FOR TUNING RESISTORS AND CAPACITORS 审中-公开
    方法和设备进行表决电阻器和电容器

    公开(公告)号：EP2005587A2

    公开(公告)日：2008-12-24

    申请号：EP07760216.7

    申请日：2007-04-05

    申请人： QUALCOMM Incorporated

    发明人： CICALINI, Alberto

    IPC分类号： H03H1/02

    CPC分类号： H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    摘要： A two-step tuning process for resistors (410) and capacitors (420) in an integrated circuit (170) is described. In the first step of the tuning process, an on-chiρ adjustable resistor (410) is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate within a target percentage determined by the external resistor and the design of the adjustable resistor (410). In the second step, an adjustable capacitor (420) is tuned based on the value of the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor (420) may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate within a target percentage determined by the accurate clock and the design of the adjustable capacitor (420). The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

    Electrical filter
    17.
    发明公开
    Electrical filter 失效
    电过滤器。

    公开(公告)号：EP0191529A2

    公开(公告)日：1986-08-20

    申请号：EP86200175.7

    申请日：1986-02-10

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Hughes, John Barry

    IPC分类号： H03H3/00 ,  H03H11/00 ,  H03H19/00

    CPC分类号： H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    摘要： A continuous time electrical filter fabricated as an integrated circuit includes capacitors (CO,CN) and resistors (R 1 ,R2). Since capacitors and resistors are difficult to integrate with accurately defined values a trimming circuit is provided which operates switches (S1-SN) to select appropriate ones of the capacitors (CN) to accurately define the cut-off frequency of the filter.
    The trimming circuit comprises a capacitor (TC2) which is charged through a resistor TR1 during a first period and which is discharged in incremental steps by capacitor (TC1). The number of incremental steps is counted by a counter (11) and transferred to a register (13). The outputs (S1-SN) of the register (13) control the switches (S1-SN). Instead of adjusting the value of the capacitors in the filter the values of the resistors may be adjusted. If this is done a convenient procedure is to short out selected portions of the resistors. More than one capacitor or resistor may be adjusted using a single counter and register.

    CALIBRATING A LOOP-FILTER OF A PHASE LOCKED LOOP
    18.
    发明授权
    CALIBRATING A LOOP-FILTER OF A PHASE LOCKED LOOP 有权

    公开(公告)号：EP1658678B1

    公开(公告)日：2018-10-24

    申请号：EP04744244.7

    申请日：2004-08-12

    申请人： Nokia Technologies Oy

    发明人： VILHONEN, Sami ,  MELAVA, Jari

    IPC分类号： H03L7/093 ,  H03H7/06 ,  H03H7/54

    CPC分类号： H03H7/54 ,  H03H7/0153 ,  H03H7/06 ,  H03H7/12 ,  H03H2210/043 ,  H03L7/0891 ,  H03L7/093

    摘要： The invention relates to a method of automatically calibrating a loop-filter of a phase locked loop, which loop-filter comprises at least one RC-filter component and is integrated on a single chip together with at least one RC-filter component of another entity than the phase locked loop. In order to simplify a calibration of the loop-filter, the method comprises tuning the at least one RC-filter component of the loop-filter based on measurements performed on the at least one RC-filter component of the other entity. The invention relates equally to an integrated circuit chip comprising means for realizing this method and to a unit including such a chip.

    Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    20.
    发明公开
    Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 审中-公开
    用于校准集成电路的可调电容的时间常数依赖于电容校准电路

    公开(公告)号：EP1962421A1

    公开(公告)日：2008-08-27

    申请号：EP07425100.0

    申请日：2007-02-23

    申请人： STMicroelectronics S.r.l.

    发明人： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Zamprogno, Marco

    IPC分类号： H03H1/02 ,  H03H7/01

    CPC分类号： H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

    摘要： A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
    - a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
    - a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
    - a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),

    characterized in that
    said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.

    摘要翻译： 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容器（C VAR（REG_BUS）），并且包括一个校准循环（RC_DEL，DFF，TG_SAR），包括： - 一个可控电容单元（RC_DEL）适合于接收控制信号（SAR_BUS）和包括至少一个 开关电容器（C_AR1，CAR_2）的阵列也可以由控制信号（SAR_BUS），单元（RC_DEL）的方式来激活正被检查，以输出由参数为特征的第一信号（OUT_DEL）上的电容的量根据 由控制信号（SAR_BUS）激活阵列（C_AR1，CAR_2）的; - 一个比较单元（DFF），其适于接收所述第一信号（OUT_DEL）评估是否所述参数是否满足预设条件，并输出比较信号（OUT_DFF）代表评估结果的一个; - 控制和定时逻辑单元（TG_SAR）适合于基于所述比较信号（OUT_DFF）接收比较信号（OUT_DFF）来改变该控制信号（SAR_BUS）表示，在这特点第一信号（OUT_DEL）是一个逻辑信号，并且 所述参数是所述第一信号的时间参数。