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    Dynamic power management in system on chips (SOC)
    13.
    发明授权
    Dynamic power management in system on chips (SOC) 有权
    对于系统级芯片（SOC）动态电源管理

    公开(公告)号：EP1677175B1

    公开(公告)日：2013-08-28

    申请号：EP05113079.7

    申请日：2005-12-29

    Applicant: ST-Ericsson SA

    Inventor： Uguen, Laurent ,  Dhiman, Gaurav ,  Kapoor, Gaurav

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.

    POWER CONSUMPTION PREDICTION METHOD FOR CLOCK-GATING INTEGRATED CIRCUIT DEVICE
    14.
    发明公开
    POWER CONSUMPTION PREDICTION METHOD FOR CLOCK-GATING INTEGRATED CIRCUIT DEVICE 审中-公开
    ÜEN UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG UNG

    公开(公告)号：EP2610702A2

    公开(公告)日：2013-07-03

    申请号：EP11820107.8

    申请日：2011-07-12

    Applicant: Yi, Joonhwan

    Inventor： Yi, Joonhwan

    IPC: G06F1/32 ,  G06F1/04

    CPC classification number: G06F1/32 ,  G06F1/3237 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5059 ,  G06F2217/62 ,  G06F2217/78 ,  Y02D10/128

    Abstract: A power consumption prediction method for an integrated circuit device is provided. The power consumption prediction method includes detecting a clock gating cell of the integrated circuit device to extract clock gating domains of the integrated circuit device, extracting a power consumption model of the integrated circuit device according to clock gating based on the extracted clock gating domains, and estimating power consumption of the integrated circuit device based on the extracted power consumption model.

    Abstract translation: 提供了一种用于集成电路器件的功耗预测方法。 功耗预测方法包括：检测集成电路器件的时钟门控单元，提取集成电路器件的时钟门控域，并根据提取的时钟选通域根据时钟选通提取集成电路器件的功耗模型; 基于所提取的功耗模型估计集成电路装置的功耗。

    DATA PROCESSOR
    15.
    发明公开
    DATA PROCESSOR 审中-公开
    数据处理器

    公开(公告)号：EP2045799A4

    公开(公告)日：2013-03-13

    申请号：EP08720626

    申请日：2008-03-27

    Applicant: PANASONIC CORP

    Inventor： NISHIDA YOICHI

    IPC: G10L19/00 ,  G06F1/26 ,  G06F1/32 ,  G11B19/00 ,  G11B20/10 ,  H03M7/30 ,  H04B14/00

    CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H04W52/0229 ,  H04W52/029 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D70/00 ,  Y02D70/24

    Abstract: In order to reduce an electric power necessary to reproduce data in real time, a data processor includes: a data input unit (10) into which data is inputted in real time; an input data storing unit (11) in which the data inputted into the data input unit (10) is stored; a signal processing unit (12) operable to read out the data stored in the input data storing unit (11), and perform signal processing of data read from the input data storing unit (11); a signal processing control unit (13) operable to control the signal processing unit (12) to have the signal processing unit (12) perform an intermittent operation by having the signal processing unit (12) perform the signal processing at a processing speed faster than a real-time processing speed; a clock/power source control unit (14) operable to reduce electric power consumption of the signal processing unit (12) and the signal processing control unit (13) by restricting either or both a clock signal and an electric power to at least one section of the signal processing unit (12) and the signal processing control unit (13) in an inactive period of the intermittent operation; and an input monitor unit (15) operable to monitor the volume of data in the input data storing unit (11), to request the clock/power source control unit (14) to remove the restriction of either or both a clock signal and an electric power to at least one section of the signal processing unit (12) and the signal processing control unit (13) on the basis of the volume of data in the input data storing unit (11), and to request the signal processing control unit (13) to move into an active period of the intermittent operation.

    Circuitry system and method for connecting synchronous clock domains of the circuitry system
    16.
    发明公开
    Circuitry system and method for connecting synchronous clock domains of the circuitry system 有权
    Schaltungssystem und Verfahren zur Verbindung同步器Taktbereiche des Schaltungssystems

    公开(公告)号：EP2360553A3

    公开(公告)日：2013-01-30

    申请号：EP11154282.5

    申请日：2011-02-14

    Applicant: Blue Wonder Communications GmbH

    Inventor： Hesse, Kay ,  Melzer, Lars

    IPC: G06F1/04 ,  G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/10 ,  G06F1/3237 ,  Y02D10/128

    Abstract: A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end. The invention is generally applicable with handshake-type bus protocols.
    The clock domain separation module of the invention allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation.

    Abstract translation: 提供时钟域分离装置和用于操作该装置的方法，用于分离片上系统（SoC）中总线系统的两个时钟域。 时钟域分离设备是一个硬件模块，用作在包含总线端的两个时钟域之间的保护。 本发明一般适用于握手型总线协议。 本发明的时钟域分离模块允许每个时钟域独立于其他时钟域的状态来切换其时钟的开启和关闭，而不会造成数据丢失或协议违规的风险。

    Information processing apparatus and branch prediction method
    18.
    发明授权
    Information processing apparatus and branch prediction method 有权
    信息处理设备和分支预测方法

    公开(公告)号：EP2261797B1

    公开(公告)日：2012-07-04

    申请号：EP10162770.1

    申请日：2010-05-13

    Applicant: Fujitsu Limited

    Inventor： Suzuki, Takashi

    IPC: G06F9/38 ,  G06F1/32

    CPC classification number: G06F9/3844 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3246 ,  Y02D10/128

    Abstract: An information processor includes a first recording unit (13) which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent branch instruction, a computation of the most recent branch instruction having been completed and a branch for the most recent branch prediction having been taken, a second recording unit (14) which stores second information indicating correspondence between an instruction address and a branch destination address of each of past branch instructions including the most recent branch instruction, computations of the past branch instructions having been completed and branches for the past branch instructions having been taken, and a control unit (12) which makes a branch prediction based on the first information or the second information, and stops supply of a clock to the second recording unit (14) and makes a branch prediction based on the first information when an instruction sequence enters a loop.

    Method and apparatus for the conditional enablement of PCI power management
    19.
    发明授权
    Method and apparatus for the conditional enablement of PCI power management 有权
    用于条件使PCI电源管理的方法和装置

    公开(公告)号：EP1383032B1

    公开(公告)日：2011-08-17

    申请号：EP03014651.8

    申请日：2003-06-26

    Applicant: Broadcom Corporation

    Inventor： Ma, Kenneth

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171

    Abstract: A method and apparatus are disclosed for conditionally enabling/disabling PCI power management in a computer-based system employing a central resource and an operating system. Non-CLKRUN# compatible PCI devices in the system are identified and whether or not the non-CLKRUN# compatible PCI devices are enabled is determined. The CLKRUN# support capability of the central resource, if available, is enabled or disabled based on, at least in part, the established status of the non-CLKRUN# compatible PCI devices. If enabled, PCI power management is provided by the CLKRUN# support capability according to the PCI CLKRUN# protocol for all CLKRUN# compatible PCI devices present in the computer-based system.

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