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公开(公告)号：EP0553733B1
公开(公告)日：2001-12-12
申请号：EP93101008.6
申请日：1993-01-22
申请人： SONY CORPORATION
发明人： Yamamoto, Iwao , Matsuno, Katsumi
CPC分类号： G06F8/66 , G06F9/328 , G06F9/3861
摘要： An electronic apparatus (10) which includes a CPU (1), a ROM (2), a RAM (3), an input port (4), a data bus (5), an address bus (6), a patching portion address register (7) and a patching interrupt vector register (8) which are connected to the data bus (5), a comparator (9) which compares a coincidence with the address stored in the address register (7) and an address on the address bus (6) and supplies an interrupt to an interrupt control portion of the CPU (1) which is also supplied with other interrupts for other processing. Further, an external storage device (20), connected to the input port (4), supplies a main program bug patching information which is stored in the RAM (3), which includes a stack area (32) in which there are saved data written in the address register (7) and the patching interrupt register (8), so that patching of program bugs can be carried out even during an interrupt.
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公开(公告)号：EP0853783B1
公开(公告)日：2001-08-16
申请号：EP96936101.3
申请日：1996-10-04
发明人： FAVOR, John, G.
CPC分类号： G06F9/382 , G06F9/30054 , G06F9/30152 , G06F9/30174 , G06F9/30185 , G06F9/30196 , G06F9/3806 , G06F9/3812 , G06F9/3816 , G06F9/3822 , G06F9/3853
摘要： An instruction decoder (220) includes an emulation code sequencer (510) and emulation code ROM (520) for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation sequencing control code (OpSeq). Branch instructions such as conditional branch instructions may be encoded into the emulation code ROM so that a second branch, in combination with the branching operation controlled by the OpSeq code, is applied to an operation code sequence. Two-way branching permits flexible branching to locations within the emulation code ROM so that memory capacity is conserved. A superscalar microprocessor (120) includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. The emulation code ROM is arranged as a matrix of multiple-operation (Op) units with each multiple-Op unit including a control field that points to a next location in the emulation code ROM. In one embodiment, the emulation code ROM is arranged to include a plurality of four-Op units, called Op quads, with each Op quad including a sequencing control field, called an OpSeq field.
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13.发明授权INSTRUCTION DECODER INCLUDING EMULATION USING INDIRECT SPECIFIERS 失效采用仿真BY INDIREKTSPEZIFIZIERER命令解码器
公开(公告)号：EP0853782B1
公开(公告)日：2001-06-27
申请号：EP96933907.6
申请日：1996-10-04
发明人： FAVOR, John, G.
CPC分类号： G06F9/382 , G06F9/30054 , G06F9/30152 , G06F9/30167 , G06F9/30174 , G06F9/324 , G06F9/3812 , G06F9/3816 , G06F9/3853
摘要： A ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address the emulation ROM, from which an operation (Op) is read. Various fields of the Op are selectively substituted from the instruction register and emulation environment registers.
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公开(公告)号：EP0715251B1
公开(公告)日：2000-07-26
申请号：EP94118741.1
申请日：1994-11-29
发明人： Staiger, Dieter E.
IPC分类号： G06F9/26
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15.发明公开A method and apparatus for operation control of memories 失效Verfahren und Vorrichtung zur Betriebssteuerung von Speichern
公开(公告)号：EP0831397A2
公开(公告)日：1998-03-25
申请号：EP97307347.1
申请日：1997-09-22
CPC分类号： G11C29/16
摘要： The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signals, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.
摘要翻译： 该方法包括在芯片上形成控制ROM，用于在控制ROM中执行操作的编程指令，以及在芯片上形成微定序器，以响应于来自外部源的微代码来执行 存储器阵列根据在控制ROM中编程的指令。 微定序器具有用于从外部源接收微码并用于将第一信号耦合到具有内置逻辑块观察（BILBO）控制的指令解码器的测试多路复用器。 具有BILBO控制的指令解码器也从控制ROM接收操作码。 具有BILBO控制的指令解码器控制子程序堆栈并提供索引信号A程序计数器多路复用器（PCM）接收操作码，用于从子程序堆栈接收第二信号，并从增量器接收第三信号。 PCM向控制ROM提供第四个信号。
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16.发明公开Synchronous semiconductor memory device having macro command storage and execution method therefor 失效Synchrone Halbleiterspeichervorrichtung mit Makrobefehlsspeichern undAusführungsverfahrendafür
公开(公告)号：EP0829804A2
公开(公告)日：1998-03-18
申请号：EP97307112.9
申请日：1997-09-12
发明人： Park, Chul-Woo , Choi, Myung-Chan
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3802 , G06F9/3869
摘要： A semiconductor memory device having a macro command function includes a macro storage section for storing a series of external instructions synchronized with a clock signal and a plurality of interval data corresponding to a number of clock pulses occurring between the external instructions. A counter is also included for counting the clock pulses and for producing an output representing a number of clock pulses occurring since an initialization of the counter, and a selecting section is included for selecting between a current external instruction synchronized with the clock signal and the external instructions read out from the macro storage section. A comparing section is included for comparing the interval data of the appropriate external instruction from the macro storage section with an output of the counter, and a macro control section is included for controlling the macro storage section in response to a macro store command so that the series of external instructions and the number of clock pulses counted by the counter are stored in the macro storage section. The macro control means also controlling the selecting section to select the macro storage section in response to a macro execute command so that the series of instructions stored in the macro storage section are sequentially read out. The macro control also produces a next command when the interval data of the read-out external instruction equals the output of the counter.
摘要翻译： 具有宏指令功能的半导体存储器件包括宏存储部分，用于存储与时钟信号同步的一系列外部指令和对应于外部指令之间出现的时钟脉冲数的多个间隔数据。 还包括一个计数器，用于对时钟脉冲进行计数，并产生表示自计数器初始化以来出现的时钟脉冲数的输出，并且包括选择部分，用于在与时钟信号同步的当前外部指令与外部 指令从宏存储部分读出。 包括比较部分，用于将来自宏存储部分的适当的外部指令的间隔数据与计数器的输出进行比较，并且包括宏控制部分，用于响应于宏存储命令来控制宏存储部分， 一系列外部指令和计数器计数的时钟脉冲数存储在宏存储部分中。 宏控制装置还响应宏执行命令控制选择部分选择宏存储部分，以便顺序地读出存储在宏存储部分中的一系列指令。 当读出的外部指令的间隔数据等于计数器的输出时，宏控制也产生下一个命令。
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公开(公告)号：EP0448127B1
公开(公告)日：1998-01-28
申请号：EP91106315.4
申请日：1985-05-07
IPC分类号： G06F9/26
CPC分类号： G06F9/264 , G06F9/268 , G06F9/30061 , G06F11/34 , G06F11/3648 , G06F13/24
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公开(公告)号：EP0813709A1
公开(公告)日：1997-12-29
申请号：EP96911211
申请日：1996-02-29
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A memory management unit (124) (MMU) includes a translation lookaside buffer (108) capable of simultaneously servicing three requests supplied to the MMU by an instruction cache (102) and two data caches (103, 104), respectively. Also, an arbiter (113) selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.
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19.发明公开Operating circuit and method for selecting signal processing commands in ADPCM system 失效驱动电路和方法，用于在ADPCM系统中选择的信号处理指令
公开(公告)号：EP0756230A3
公开(公告)日：1997-10-15
申请号：EP95120263.9
申请日：1995-12-21
发明人： Goto, Koji , Kinoshita, Satoru
CPC分类号： G06F9/324 , G06F9/30058
摘要： The invention provides an operating circuit which carries out conditional branch to judge which value level an operated result of ALU (33) includes during one machine cycle, using an address unit (29) comprised of a hardware, which realizes shorter processing time and low power consumption. The operating circuit for sequentially carrying out calculations according to the command codes in a command ROM (28) comprises: a result register (1) for storing and outputting an output result of the ALU (33); value level judgement means (7) for judging which value level an output of the result register (1) is included in; latch means (15) for storing a current value of a program counter (26); adder means (18) for calculating a next value of program counter (26) by adding a value level judgement result from the value level judgement means (7) and a current value of program counter (26) stored in the latch means (15); and a first selector means (23) for selecting an added result and for deciding a next command address in the command ROM (28), wherein conditional branch is carried out to a command address which is corresponding to a value obtained by the calculated result from ALU.
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公开(公告)号：EP0374598B1
公开(公告)日：1997-05-02
申请号：EP89122558.3
申请日：1989-12-07
CPC分类号： G06F9/3836 , G06F9/262 , G06F9/28 , G06F9/3861
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