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公开(公告)号：EP3618284B1
公开(公告)日：2023-11-01
申请号：EP18192120.6
申请日：2018-08-31
发明人： Fan, Hao , Pertijs, Michiel , Buter, Berry
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公开(公告)号：EP3618284A1
公开(公告)日：2020-03-04
申请号：EP18192120.6
申请日：2018-08-31
申请人： NXP B.V.
发明人： Fan,, Hao , Pertijs,, Michiel , Buter,, Berry
摘要： A capacitance-to-digital-converter comprising: a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.
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13.发明公开METHOD AND APPARATUS FOR INDIRECT CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 审中-公开方法和装置的电压值在数字WORD间接转换
公开(公告)号：EP3145087A1
公开(公告)日：2017-03-22
申请号：EP15201443.7
申请日：2015-12-18
摘要： A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval (T) is mapped to a difference of a length of a reference time (RT) and a length of a signal time (ST), while the reference time (RT) is generated from an instant (t 1 ) when the beginning of the time interval (T) is detected by the use the control module (CM), and the signal time (ST) is generated from an instant (t 2 ) when the end of the time interval (T) is detected by the use the control module (CM), whereas generation of the reference time (RT) and the signal time (ST) is terminated at the same instant (t 3 ).
摘要翻译： 一种用于电压值的数字字通过一个采样电容器的输入电压的源极并联连接在输入电压的采样由...组成间接变换方法，并且在输入电压的采样值映射到的时间间隔下 ，并在通过使用特征的控制模块所做的时间间隔（T）被映射到的一个基准时间的长度（RT）的差和一个长度为n位输出数字字的一个相应的值的分配 信号时间（ST），而该基准时间（RT）从在当通过使用控制模块（CM），和信号时检测到的时间间隔（T）的开始时刻（T 1）中生成（ST ）从（在时刻t 2）当通过使用控制模块（CM）检测到的时间间隔（T）的端部，而生成的基准时间（RT）和所述信号 - 时间（ST）被终止产生 在同一时刻（T 3）。
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14.发明公开ASYNCHRONOUS SERIAL ANALOG-TO-DIGITAL CONVERTER METHODOLOGY HAVING DYNAMIC ADJUSTMENT OF THE BANDWITH 有权FOR SERIAL方法，具有动态带宽异步模数转换停产
公开(公告)号：EP1530823A1
公开(公告)日：2005-05-18
申请号：EP03766396.0
申请日：2003-07-31
IPC分类号： H03M1/54
摘要： A new methodology is disclosed to convert analog electric signals into digital data. The method provides a serial scheme without pre-definition of the number of bits (dynamic range). It allows digital processing of the input signal without sampling and holding of the input signal. Processing of the input signal is clock-less and asynchronously dependent on the time-evolution of the input signal itself. Thereby, a programmable, dynamic adjustment of bandwidth (product of dynamic range and speed of conversion) of the analog-to-digital conversion process can be achieved depending on the characteristics of the input signal. Dynamic adjustment of the bandwidth is accomplished by digitally controlling a 'threshold' value at the input capacitor of the comparator, which when met by the input signal, triggers a transition at the output of the comparator.
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公开(公告)号：EP0212898A2
公开(公告)日：1987-03-04
申请号：EP86305966.3
申请日：1986-08-01
IPC分类号： H03M1/54
CPC分类号： H03M1/54
摘要： A converter for converting an analog signal to a digital pulse comprises a switching capacitor (10) which is charged by a differential analog signal supplied to the switching capacitor (10) over an input circuit (12). The capacitor (10) is discharged over an output circuit (14) with the aid of a constant current supply (44). The charge level of the capacitor (10) is proportional to the analog signal so that the time it takes the capacitor to discharge to a selected low charge level is proportional to the analog signal. This time period is used by a microprocessor (50) to generate a digital pulse having a pulse width equal to the discharge time for the capacitor (10). The microprocessor (50) also selectively connects the input and output circuits (12, 14) to the capacitor (10) for respectively charging and discharging the capacitor.
摘要翻译： 用于将模拟信号转换为数字脉冲的A转换器包括通过输入电路（12）提供给开关电容器（10）的差动模拟信号而充电的开关电容器（10）。 借助于恒定电流源（44），电容器（10）在输出电路（14）上放电。 电容器（10）的充电电平与模拟信号成比例，使得电容器放电到选定的低充电电平所花费的时间与模拟信号成比例。 这个时间段由微处理器（50）使用以产生脉冲宽度等于电容器（10）的放电时间的数字脉冲。 微处理器（50）还选择性地将输入和输出电路（12,14）连接到电容器（10），以分别对电容器充电和放电。
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公开(公告)号：EP4040682A1
公开(公告)日：2022-08-10
申请号：EP21155525.5
申请日：2021-02-05
申请人： Imec VZW , Katholieke Universiteit Leuven KU Leuven Research & Development , Stichting IMEC Nederland
摘要： An analog-to-digital converter, ADC, circuitry, comprises: an integrator (102; 202) connected to a capacitor (110; 210a, 210b), the integrator (102; 202) being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator (120; 220) for comparing integrator output to the threshold; and a timer (150; 250) for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry (100; 200) further comprising a feedforward noise shaping loop (130; 130a, 130b; 230a, 230b) configured to store a quantization error signal based on digitizing a first sample, the comparator (120; 220) being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.
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公开(公告)号：EP2751927B1
公开(公告)日：2021-02-24
申请号：EP12788810.5
申请日：2012-05-21
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公开(公告)号：EP3422581A1
公开(公告)日：2019-01-02
申请号：EP17897122.2
申请日：2017-02-17
发明人： ZHANG, Mengwen , ZHAN, Chang
摘要： Embodiments of the present invention provide a correlated double sampling integrating circuit, including: a sampling and holding module, an energy storage unit and a feedback module; where the sampling and holding module is configured to perform sampling and holding for different input signals, the energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals (for example, node voltages), and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to be consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. Therefore, the correlated double sampling integrating circuit eliminates the noise caused by 1/f noise of the operational amplifier and noise caused by mismatch voltage, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations.
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19.发明公开METHOD AND APPARATUS FOR PERFORMING DATA CONVERSION WITH NON-UNIFORM QUANTIZATION 审中-公开方法和设备进行数据转换与凸凹QUANTIZE实现
公开(公告)号：EP2751927A4
公开(公告)日：2015-07-08
申请号：EP12788810
申请日：2012-05-21
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20.发明授权ASYNCHRONOUS SERIAL ANALOG-TO-DIGITAL CONVERTER METHODOLOGY HAVING DYNAMIC ADJUSTMENT OF THE BANDWITH 有权FOR SERIAL方法，具有动态带宽异步模数转换停产
公开(公告)号：EP1530823B1
公开(公告)日：2007-05-30
申请号：EP03766396.0
申请日：2003-07-31
IPC分类号： H03M1/54
摘要： A new methodology is disclosed to convert analog electric signals into digital data. The method provides a serial scheme without pre-definition of the number of bits (dynamic range). It allows digital processing of the input signal without sampling and holding of the input signal. Processing of the input signal is clock-less and asynchronously dependent on the time-evolution of the input signal itself. Thereby, a programmable, dynamic adjustment of bandwidth (product of dynamic range and speed of conversion) of the analog-to-digital conversion process can be achieved depending on the characteristics of the input signal. Dynamic adjustment of the bandwidth is accomplished by digitally controlling a 'threshold' value at the input capacitor of the comparator, which when met by the input signal, triggers a transition at the output of the comparator.
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