SERIAL BIT RATE CONVERTER FOR A TDM SWITCHING MATRIX
    21.
    发明公开
    SERIAL BIT RATE CONVERTER FOR A TDM SWITCHING MATRIX 失效
    串行比特率转换用于时间复用VERMITTLUNGSKOPPLER

    公开(公告)号:EP0710426A1

    公开(公告)日:1996-05-08

    申请号:EP94921555.0

    申请日:1994-07-13

    申请人: MITEL CORPORATION

    IPC分类号: H03M9 H04J3 H04Q11

    CPC分类号: H04J3/047 H04Q11/08

    摘要: A time division switching matrix capable of effecting rate conversion comprises a plurality of serial inputs for connection to respective serial input links, each capable of carrying time division multiplexed PCM channels, a plurality of serial outputs for connection to respective serial output links, each capable of carrying time division multiplexed PCM channels, and a serial-to-parallel converter associated with each input for converting a serial input stream to parallel format, each said serial-to-parallel converter being independently configurable to produce the same net parallel throughput regardless of the bit rate of the associated input link. The output side of the switching matrix can be similarly configured.

    REGULATED AUXILIARY POWER SUPPLY
    22.
    发明授权
    REGULATED AUXILIARY POWER SUPPLY 失效
    控制的辅助电源

    公开(公告)号:EP0607246B1

    公开(公告)日:1995-12-13

    申请号:EP92921197.7

    申请日:1992-10-09

    申请人: MITEL CORPORATION

    发明人: LAVRISA, Tom

    IPC分类号: H02M3/335 G05F1/56 G06F1/26

    摘要: An auxiliary regulated power supply is described for use in a system having a main load directly connected to a main regulated power supply and an auxiliary load connected to the main regulated power supply by a line in which a voltage drop occurs. The auxiliary regulated power supply comprises a pair of input terminals for connection to the line, a pair of terminals for connection to a voltage source, a pair of output terminals for connection to the auxiliary load, a circuit for sensing the voltage at the output terminals, and an arrangement for boosting the output voltage at the output terminals from a secondary voltage source as necessary to maintain it at a level appropriate for the auxiliary load.

    WIRELESS INTERFACE
    23.
    发明公开
    WIRELESS INTERFACE 失效
    无线接口。

    公开(公告)号:EP0610287A1

    公开(公告)日:1994-08-17

    申请号:EP92921893.0

    申请日:1992-10-22

    申请人: MITEL CORPORATION

    发明人: MEIER, Rolf, G.

    IPC分类号: H04W88

    CPC分类号: H04W88/08

    摘要: Un système de téléphone sans fil comprend: un central privé connecté par câble à au moins une station de base permettant de communiquer par liaison de base permettant de communiquer par liaison radio avec des téléphones mobiles; un émetteur-récepteur pour signaux audio et données transmis sur le câble reliant ce central public et la station de base; et un émetteur-récepteur pour signaux audio et données transmis sur la liaison radio reliant la station de base et les téléphones mobiles. Dans la station de base, on trouve un séparateur concernant les voies entrantes pour signaux audio et données, un dispositif combinant les signaux audio et données qui sortent pour être émis par la station de base et un autre qui interprète ces signaux de données afin de les envoyer à la station de base, s'il lui sont destinés, ou qui les transmet via cette station de base vers l'appareil récepteur.

    POWER AMPLIFIER WITH QUIESCENT CURRENT CONTROL
    24.
    发明公开
    POWER AMPLIFIER WITH QUIESCENT CURRENT CONTROL 失效
    功率放大器与信号相关的静态电流设置。

    公开(公告)号:EP0602163A1

    公开(公告)日:1994-06-22

    申请号:EP92919601.0

    申请日:1992-09-03

    申请人: MITEL CORPORATION

    发明人: MOLNAR, Gerald

    IPC分类号: H03F3

    摘要: Un amplificateur de puissance comprend un étage d'entrée comportant un amplificateur entièrement différentiel avec des entrées et des sorties différentielles, et un circuit de contrôle du retour fonctionnant en boucle fermée et à haute impédance séparant les signaux de contrôle de retour en boucle fermée des sorties différentielles. L'étage de sortie de chaque sortie différentielle de l'étage d'entrée comprend un amplificateur de classe AB ayant des suiveurs de source s'interfaçant avec l'amplificateur entièrement différentiel. Un circuit de contrôle de la tension de sortie fonctionnant en mode commun maintient la tension de sortie en mode commun de l'amplificateur de classe AB à un niveau voulu. Un régulateur de courant de repos comprend un circuit reproduisant le comportement de l'un des suiveurs de source pour dériver un signal de régulation en maintenant le courant de repos des transistors de sortie à une valeur désirée.

    STABILIZATION OF THE INTERFACE BETWEEN TiN AND A1 ALLOYS
    25.
    发明公开
    STABILIZATION OF THE INTERFACE BETWEEN TiN AND A1 ALLOYS 失效
    边界之间的锡和铝合金镇定

    公开(公告)号:EP0902968A1

    公开(公告)日:1999-03-24

    申请号:EP97945682.0

    申请日:1997-11-26

    申请人: MITEL CORPORATION

    IPC分类号: H01L21

    CPC分类号: H01L21/76846 H01L21/76856

    摘要: A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.

    Modulated local oscillator
    26.
    发明公开
    Modulated local oscillator 审中-公开
    ModulierterÜberlagerungsoszillator

    公开(公告)号:EP0899868A1

    公开(公告)日:1999-03-03

    申请号:EP98306821.4

    申请日:1998-08-26

    申请人: MITEL CORPORATION

    IPC分类号: H03D7/00

    CPC分类号: H03D7/00

    摘要: A method of performing a frequency conversion of a radio frequency (RF) information signal by mixing the information signal with a modulated signal from local oscillator. The local oscillator signal is modulated with a periodic, coded or pseudo-random modulating signal. A system for generating an intermediate frequency (IF) output signal from the information signal is also provided.

    摘要翻译: 通过将信息信号与来自本地振荡器的调制信号混合来执行射频(RF)信息信号的频率转换的方法。 本地振荡器信号用周期性,编码或伪随机调制信号进行调制。 还提供了一种用于从信息信号产生中频(IF)输出信号的系统。

    Time-slot switch
    28.
    发明公开
    Time-slot switch 失效
    Zeitkanalschalter

    公开(公告)号:EP0817528A2

    公开(公告)日:1998-01-07

    申请号:EP97304489.4

    申请日:1997-06-25

    申请人: MITEL CORPORATION

    IPC分类号: H04Q11/08

    CPC分类号: H04Q11/08

    摘要: A digital switch array, comprises a serial input bus providing a plurality of input streams (2a, 2b) each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams (3a, 3b), each defining a plurality of time division multiplexed output channels, and an array of digital switches (1a, 1b, 1c, 1d) arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches (1a, 1b, 1c, 1d) are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device (9, 10) for each output timeslot so that when the enabling device (9, 10) is enabled the associated output timeslot is driven, and at least first and second enabling inputs (4a, 4b) which when simultaneously activated cause the enabling means to become enabled. An array of activation lines (5a, 5b, 6a, 6b) are arranged in rows and columns. The respective rows (5a, 5b) of activation lines are connected to the first enabling inputs (4a) of each row of the digital switches (1a, 1b, 1c, 1d) and the respective columns (6a, 6b) of activation lines are connected to the second enabling inputs (4b) of each column of the digital switches (la, 1b, 1c, 1d). A selected row (5a, 5b) and column (6a, 6b) of the activation lines can be simultaneously activated so that the enabling device (9, 10) of the digital switch (1a, 1b, 1c, 1d) whose first input is connected to the activated row (5a, 5b) and whose second input is connected to the activated column (6a, 6b) becomes enabled.

    摘要翻译: 数字开关阵列包括提供多个输入流(2a,2b)的串行输入总线,每个输入流定义多个时分多路复用输入通道,串行输出总线提供多个输出流(3a,3b),每个定义 多个时分复用输出通道,以及排列成行和列的数字开关(1a,1b,1c,1d)阵列。 每行连接到相应的输入流组,并且每列连接到相应的输出流组。 数字开关(1a,1b,1c,1d)能够在任何输入和任何输出通道之间执行时隙交换。 每个数字开关包括用于每个输出时隙的使能装置(9,10),使得当使能装置(9,10)被使能时,相关联的输出时隙被驱动,并且至少第一和第二使能输入(4a,4b) 当同时激活时,使启用手段成为启用状态。 激活线阵列(5a,5b,6a,6b)以行和列排列。 激活线的相应行(5a,5b)连接到每行数字开关(1a,1b,1c,1d)的第一使能输入(4a),并且激活线的相应列(6a,6b) 连接到数字开关(1a,1b,1c,1d)的每列的第二使能输入(4b)。 可以同时激活激活线的选定行(5a,5b)和列(6a,6b),使得其第一输入的数字开关(1a,1b,1c,1d)的使能装置(9,10) 连接到激活的行(5a,5b)并且其第二输入连接到激活的列(6a,6b)变得有效。

    DIGITAL PHASE LOCKED LOOP
    29.
    发明公开
    DIGITAL PHASE LOCKED LOOP 失效
    数字锁相环路

    公开(公告)号:EP0772912A2

    公开(公告)日:1997-05-14

    申请号:EP95929688.0

    申请日:1995-07-20

    申请人: MITEL CORPORATION

    IPC分类号: H03L7

    CPC分类号: H03L7/081

    摘要: A digital phase locked loop is for recovering a stable clock signal from at least one input signal subject to jitter is disclosed. The loop comprises a digital input circuit receiving at least one input signal, a digital controlled oscillator for generating an output signal at a desired frequency and a control signal representing the time error in said output signal, a stable local oscillator for providing clock signals to the digital controlled oscillator, and a tapped delay line for receiving the output signal of the digital controlled oscillator. The tapped delay line comprises a plurality of buffers each introducing a delay of less than one clock cycle of the digital controlled oscillator. The tapped delay line produces an output signal from a tap determined by the control signal. A digital phase comparator receives at least one input signal from the input circuit and the output signal from the tapped delay line to generate a digital input signal controlling the digital controlled oscillator.

    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES
    30.
    发明公开
    HIGH PERFORMANCE PASSIVATION FOR SEMICONDUCTOR DEVICES 失效
    钝化FOR半导体布置高性能。

    公开(公告)号:EP0598795A1

    公开(公告)日:1994-06-01

    申请号:EP92917204.0

    申请日:1992-08-10

    申请人: MITEL CORPORATION

    发明人: OUELLET, Luc

    IPC分类号: H01L21 H01L23

    摘要: PCT No. PCT/CA92/00346 Sec. 371 Date Feb. 23, 1994 Sec. 102(e) Date Feb. 23, 1994 PCT Filed Aug. 10, 1992 PCT Pub. No. WO93/04501 PCT Pub. Date Mar. 4, 1993A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.