利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.009 秒)

    Grounded inductance circuit using gyrator circuit
    2.
    发明公开
    Grounded inductance circuit using gyrator circuit 失效
    Eine Gyratorschaltung verwendende geerdete Induktschaltung

    公开(公告)号：EP0746096A1

    公开(公告)日：1996-12-04

    申请号：EP96304007.6

    申请日：1996-06-03

    申请人： NEC CORPORATION

    发明人： Fujii, Tomohiro, c/o NEC Corporation

    IPC分类号： H03H11/50

    CPC分类号： H03H11/50 ,  H03F1/3211 ,  H03F3/45085 ,  H03F2203/45371 ,  H03F2203/45508 ,  H03F2203/45648 ,  H03F2203/45732

    摘要： The grounded inductance circuit utilizing a gyrator circuit includes a first operational transconductance amplifier, a second operational transconductance amplifier and a first capacitor. A first output terminal of the first operational transconductance amplifier is connected to a first input terminal of the second operational trans-conductance amplifier, and a second output terminal of the first operational transconductance amplifier is connected to a second input terminal of the second operational transconductance amplifier. A first output terminal of the second operational transconductance amplifier is connected to a second input terminal of the first operational transconductance amplifier and a second output terminal of the second operational transconductance amplifier is connected to a first input terminal of the first operational trans-conductance amplifier. The second input terminal of the first operational transconductance amplifier and the first input terminal of the second operational transconductance amplifier are connected to each other and the junction of the two input terminals is applied with a predetermined dc bias voltage with respect to the ground potential. The capacitor is connected between the junction and the second input terminal of the second operational transconductance amplifier. An ac signal is applied between the first input terminal of the first operational transconductance amplifier and the ground potential.

    摘要翻译： 利用回转器电路的接地电感电路包括第一运算跨导放大器，第二运算跨导放大器和第一电容器。 第一运算跨导放大器的第一输出端连接到第二运算跨导放大器的第一输入端，第一运算跨导放大器的第二输出端连接到第二运算跨导放大器的第二输入端 。 第二运算跨导放大器的第一输出端连接到第一运算跨导放大器的第二输入端，第二运算跨导放大器的第二输出端连接到第一运算跨导放大器的第一输入端。 第一操作跨导放大器的第二输入端和第二运算跨导放大器的第一输入端彼此连接，并且两个输入端的结点相对于地电位施加预定的直流偏置电压。 电容器连接在第二运算跨导放大器的结和第二输入端之间。 在第一运算跨导放大器的第一输入端与地电位之间施加交流信号。

    High gain differential amplifier capable of reducing offset voltage
    3.
    发明公开
    High gain differential amplifier capable of reducing offset voltage 失效
    具有高增益，能够DC的差分放大器的偏移电压的降低。

    公开(公告)号：EP0630102A3

    公开(公告)日：1995-08-23

    申请号：EP94304269.7

    申请日：1994-06-14

    申请人： NEC CORPORATION

    发明人： Sone, Kazuya, c/o NEC CORPORATION

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/45085 ,  H03F3/45089 ,  H03F3/45183 ,  H03F2203/45024 ,  H03F2203/45224 ,  H03F2203/45244 ,  H03F2203/45471 ,  H03F2203/45732

    摘要： A high gain differential amplifier including a differential transistor pair (M₁, M₂) having first and second transistors (M₁, M₂) whose gates are connected to first and second input terminals (t₁, t₂); a current mirror circuit wherein the drain of the transistor (M₁) is connected to an output terminal; a transistor (M₅) whose gate and drain are connected to the drain of transistor (M₁) and output terminal of the current mirror circuit, and to the output terminal (t₃) and the drain of transistor (M₂), respectively; a transistor (M₆) whose drain and gate are connected to an input terminal of the current mirror circuit, and to a bias power supply terminal, respectively; and constant-current source (I₁, I₂) which are connected to the common sources of differential transistor pair (M₁, M₂) and a source of the transistor (M₆), respectively. The addition of the sixth transistor (M₆) permits a voltage between the drain and source of the third and fourth transistors (M₃, M₄) to be nearly equal. As a result, a drain current ratio between the third and fourth transistors (M₃, M₄) can be precisely determined and thus an input offset voltage can be reduced to nearly zero.

    Operational amplifier circuit having wide operating range
    4.
    发明公开
    Operational amplifier circuit having wide operating range 失效
    Betriebsbereich。

    公开(公告)号：EP0259879A2

    公开(公告)日：1988-03-16

    申请号：EP87113261.9

    申请日：1987-09-10

    申请人： NEC CORPORATION

    发明人： Yukawa, Akira c/o NEC Corporation

    IPC分类号： H03F3/45 ,  H03F3/30

    CPC分类号： H03F3/4521 ,  H03F3/3028 ,  H03F3/45219 ,  H03F3/45237 ,  H03F3/45708 ,  H03F2200/153 ,  H03F2203/45508 ,  H03F2203/45664 ,  H03F2203/45732

    摘要： An operational amplifier circuit operable with a common-­mode input voltage variable over a substantially full range between given source voltages, wherein complementary first and second differential transistor pairs each consisting of transistors having current input terminals connected together are arranged with current mirror circuits and constant-current source devices so that the first differential transistor pair is turned off and the second differential transistor pair operates as input devices for a load circuit when the common-­mode input voltage approximates the lower sopurce voltage. An increase in the common-mode input voltage causes the first differential transistor pair to turn on and gives rise to a decrease in the current flowing through the second differen­tial transistor pair, in which instance the first differential transistor pair compensates for the reduction in the current through the second differential transistor pair by the action of the current mirror circuit associated with the two transis­tor pairs. The voltage applied to the load device is main­tained constant without respect to the common-mode input voltage supplied to the differential transistor pairs so that there are no noises generated during transition of the common-­mode input voltage through a certail voltage level.

    摘要翻译： 一种运算放大器电路，可在给定源极电压之间的基本上全范围内以共模输入电压变化进行操作，其中互补的第一和第二差分晶体管对每个由具有连接在一起的电流输入端的晶体管组成， 电流源装置，使得当共模输入电压接近较低的抽吸电压时，第一差分晶体管对被关断，第二差分晶体管对作为负载电路的输入装置工作。 共模输入电压的增加导致第一差分晶体管对导通，并且导致流经第二差分晶体管对的电流减小，其中第一差分晶体管对补偿电流的减小 通过与两个晶体管对相关联的电流镜电路的作用通过第二差分晶体管对。 施加到负载装置的电压保持恒定，而不依赖于提供给差分晶体管对的共模输入电压，使得在通过认证电压电平的共模输入电压的转变期间不产生噪声。

    CONFIGURABLE TRANSCEIVER CIRCUIT ARCHITECTURE
    5.
    发明公开
    CONFIGURABLE TRANSCEIVER CIRCUIT ARCHITECTURE 有权
    KONFIGURIERBARE SENDER /EMPFÄNGER-SCHALTUNGSARCHITEKTUR

    公开(公告)号：EP3084976A4

    公开(公告)日：2017-05-31

    申请号：EP13899443

    申请日：2013-12-20

    申请人： INTEL CORP

    发明人： GAO MIAOBIN ,  KRAUSE CHRISTINE M ,  WU HIU-CHIN ,  CHENG HENGJU

    IPC分类号： H04B3/02

    CPC分类号： H03F3/45475 ,  H01L23/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/0002 ,  H03F1/34 ,  H03F3/087 ,  H03F3/45183 ,  H03F2203/45112 ,  H03F2203/45206 ,  H03F2203/45288 ,  H03F2203/45528 ,  H03F2203/45641 ,  H03F2203/45646 ,  H03F2203/45674 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03F2203/45732 ,  H04B3/02 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Techniques and mechanisms for providing signal communication with a configurable transceiver circuit. In an embodiment, an integrated circuit comprises transceiver circuitry including an output stage and current mirror circuitry. The output stage is coupled to receive a differential signal pair and to provide at least one output signal based on the differential signal pair. In another embodiment, configuration logic is operable to select between a first mode and a second mode of the transceiver circuit. The first mode includes the current mirror circuitry being disabled from providing a current signal to the output stage, and a first circuit path being closed to provide voltage to the output stage. The second mode includes the first circuit path being open and the current mirror circuitry being enabled to provide a current signal to the output stage.

    摘要翻译： 用可配置收发器电路提供信号通信的技术和机制。 在一个实施例中，集成电路包括包括输出级和电流镜像电路的收发器电路。 输出级被耦合以接收差分信号对并且基于差分信号对提供至少一个输出信号。 在另一个实施例中，配置逻辑可操作以在收发器电路的第一模式和第二模式之间进行选择。 第一模式包括禁止电流镜像电路向输出级提供电流信号，并且闭合第一电路路径以向输出级提供电压。 第二模式包括第一电路路径断开并且电流镜像电路被启用以向输出级提供电流信号。

    ELECTRONIC CIRCUIT FOR PROVIDING A DESIRED COMMON MODE VOLTAGE TO A DIFFERENTIAL OUTPUT OF AN AMPLIFIER STAGE
    6.
    发明公开
    ELECTRONIC CIRCUIT FOR PROVIDING A DESIRED COMMON MODE VOLTAGE TO A DIFFERENTIAL OUTPUT OF AN AMPLIFIER STAGE 审中-公开
    电子线路创建一个共模电压加强剂的差动输出

    公开(公告)号：EP1277276A1

    公开(公告)日：2003-01-22

    申请号：EP01936135.1

    申请日：2001-03-22

    申请人： Koninklijke Philips Electronics N.V.

    发明人： BLANKEN, Pieter, G. ,  MENTEN, Stefan, E., J.

    IPC分类号： H03F3/45 ,  H03F1/22

    CPC分类号： H03F3/45659 ,  H03F1/223 ,  H03F2203/45636 ,  H03F2203/45732

    摘要： An electronic circuit for supplying a common mode voltage to a differential output of an amplifier stage (AMPSTG). The common mode voltage at the terminals (1) and (2) is approximately equal to the reference voltage (VCM). Transistors (T1 - T4) are biased in their linear region whereas transistors (T5 - T8) are biased in their saturation region. In order to choose the lowest possible reference voltage (VCM), the dimensioning of the transistors (T1 - T4) is such that the currents through the transistors (T1 - T3) have equal current densities, and the current through the transistor (T4) has a current density which is a factor N smaller than the former current densities. The factor N is determined by the ratio of the nominal value of the current through the transistor (T1) and the minimum value of the current through the transistor (T1).

    High gain differential amplifier capable of reducing offset voltage
    10.
    发明公开
    High gain differential amplifier capable of reducing offset voltage 失效
    Differentialzverstärkermit hoherVerstärkung，fähigzur Offset-Gleichspannungsverminderung。

    公开(公告)号：EP0630102A2

    公开(公告)日：1994-12-21

    申请号：EP94304269.7

    申请日：1994-06-14

    申请人： NEC CORPORATION

    发明人： Sone, Kazuya, c/o NEC CORPORATION

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/45085 ,  H03F3/45089 ,  H03F3/45183 ,  H03F2203/45024 ,  H03F2203/45224 ,  H03F2203/45244 ,  H03F2203/45471 ,  H03F2203/45732

    摘要： A high gain differential amplifier including a differential transistor pair (M₁, M₂) having first and second transistors (M₁, M₂) whose gates are connected to first and second input terminals (t₁, t₂); a current mirror circuit wherein the drain of the transistor (M₁) is connected to an output terminal; a transistor (M₅) whose gate and drain are connected to the drain of transistor (M₁) and output terminal of the current mirror circuit, and to the output terminal (t₃) and the drain of transistor (M₂), respectively; a transistor (M₆) whose drain and gate are connected to an input terminal of the current mirror circuit, and to a bias power supply terminal, respectively; and constant-current source (I₁, I₂) which are connected to the common sources of differential transistor pair (M₁, M₂) and a source of the transistor (M₆), respectively. The addition of the sixth transistor (M₆) permits a voltage between the drain and source of the third and fourth transistors (M₃, M₄) to be nearly equal. As a result, a drain current ratio between the third and fourth transistors (M₃, M₄) can be precisely determined and thus an input offset voltage can be reduced to nearly zero.

    摘要翻译： 一种高增益差分放大器，包括具有栅极连接到第一和第二输入端（t1，t2）的第一和第二晶体管（M1，M2）的差分晶体管对（M1，M2）; 电流镜电路，其中晶体管（M1）的漏极连接到输出端; 晶体管（M5）的栅极和漏极分别连接到晶体管（M1）的漏极和电流镜像电路的输出端，并分别连接到晶体管（M2）的输出端子（t3）和漏极; 分别将漏极和栅极连接到电流镜电路的输入端子的晶体管（M6）和偏置电源端子; 和连接到差分晶体管对（M1，M2）的公共源和晶体管（M6）的源极的恒流源（I1，I2）。 第六晶体管（M6）的添加允许第三和第四晶体管（M3，M4）的漏极和源极之间的电压几乎相等。 结果，可以精确地确定第三和第四晶体管（M3，M4）之间的漏极电流比，因此输入偏移电压可以降低到几乎为零。