公开(公告)号：EP1913468B1

公开(公告)日：2017-10-18

申请号：EP06789683.7

申请日：2006-08-09

申请人： Qualcomm Incorporated

发明人： DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  BURDA, Gregory, Christopher

IPC分类号： G06F9/30

CPC分类号： G06F9/30105 ,  G06F9/30141

公开(公告)号：EP1974254B1

公开(公告)日：2012-06-06

申请号：EP07717333.4

申请日：2007-01-22

申请人： QUALCOMM Incorporated

发明人： DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/318

CPC分类号： G06F9/30072 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/3016 ,  G06F9/30167

摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

摘要翻译： 提供了一种包括流水线操作方法的方法和装置，所述方法包括检测指定至少一个操作数的指令，所述指令要从至少两个操作数组中选择，所述操作数中的至少一个可能在流水线中飞行，确定 由指令指定的操作数选择标准，评估操作数选择标准以从至少两个操作数的组中选择至少一个操作数，并且一旦所选择的至少一个操作数可用，则提交执行指令，而不等待非操作数 被选择的操作数变得可用。

公开(公告)号：EP1941513B1

公开(公告)日：2010-11-10

申请号：EP06846190.4

申请日：2006-10-30

申请人： QUALCOMM Incorporated

发明人： PHAN, Michael, ThaiThanh ,  CHAI, Chiaming ,  BRIDGES, Jeffrey, Todd ,  FISCHER, Jeffrey, Herbert

IPC分类号： G11C15/04

CPC分类号： G11C15/00 ,  G11C8/12 ,  G11C15/04

摘要： A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.

公开(公告)号：EP2183657A2

公开(公告)日：2010-05-12

申请号：EP08796621.4

申请日：2008-07-25

申请人： QUALCOMM Incorporated

发明人： HOFMANN, Richard, Gerard ,  BRIDGES, Jeffrey, Todd

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.

公开(公告)号：EP1934754A1

公开(公告)日：2008-06-25

申请号：EP06815156.2

申请日：2006-09-21

申请人： Qualcomm Incorporated

发明人： STEMPEL, Brian, Michael ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne ,  CLANCY, Robert, Douglas ,  AUGSBURG, Victor, Roberts

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.

公开(公告)号：EP1910919A2

公开(公告)日：2008-04-16

申请号：EP06788854.5

申请日：2006-07-26

申请人： Qualcomm Incorporated

发明人： BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30149 ,  G06F9/3816 ,  G06F9/382

摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.

公开(公告)号：EP1869547A2

公开(公告)日：2007-12-26

申请号：EP06750153.6

申请日：2006-04-14

申请人： Qualcomm Incorporated

发明人： SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC分类号： G06F9/38

CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

公开(公告)号：EP1853998A1

公开(公告)日：2007-11-14

申请号：EP06737321.7

申请日：2006-03-06

申请人： QUALCOMM INCORPORATED

发明人： DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/3001 ,  G06F9/30072

摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.