公开(公告)号：EP1192538A2

公开(公告)日：2002-04-03

申请号：EP00922226.6

申请日：2000-04-14

申请人： Sun Microsystems, Inc.

发明人： SAULSBURY, Ashley ,  RICE, Daniel, S.

IPC分类号： G06F9/46

CPC分类号： G06F9/463 ,  G06F9/3832

摘要： A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.

公开(公告)号：EP0594377A3

公开(公告)日：1994-09-28

申请号：EP93308259.6

申请日：1993-10-18

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Poterek, Thomas J. ,  Broseghini, James L.

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

摘要： A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the re-stacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.

公开(公告)号：EP0550286A2

公开(公告)日：1993-07-07

申请号：EP92311898.8

申请日：1992-12-31

申请人： AMDAHL CORPORATION

发明人： Magee, Stephen C. ,  Lipman, Peter H.

IPC分类号： G06F9/46 ,  G06F11/34 ,  G06F9/44

CPC分类号： G06F9/4843 ,  G06F9/463

摘要： A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-level MP sync is used since the target CPUs must be in between units of operation when the updates occur since a unit of operation can be one instruction or it can be many instructions that together emulate one instruction. Two level MP sync allows CPUs that are going to be serialized to continue to process single instructions (no emulation code) while other target CPUs are in emulation mode.

摘要翻译： 多处理器（MP）计算机系统，允许目标CPU继续处理指令，而其他目标CPU正在处理仿真代码的指令，以在同步之前到达其域操作单元的结束。 使用两级MP同步，因为当更新发生时，目标CPU必须在操作单元之间，因为操作单元可以是一个指令，或者它可以是一起模拟一个指令的许多指令。 两级MP同步允许将被序列化的CPU继续处理单个指令（无仿真代码），而其他目标CPU处于仿真模式。

公开(公告)号：EP0206335A3

公开(公告)日：1988-09-21

申请号：EP86108686

申请日：1986-06-25

申请人： NEC CORPORATION

发明人： Matsumoto, Hajime

IPC分类号： G06F09/46

CPC分类号： G06F9/4812 ,  G06F9/4486 ,  G06F9/463

摘要： The invention relates to an interruption mechanism for a data processing system. The interruption mechanism comprises an execution processing unit (1) and a memory unit (2). The execution processing unit (1) includes a basic processor status storage (13), an extended processor status storage (14), current and new processor status block pointer storages (11, 12), and an interruption control section (17). Following the acceptance of interruption request, the interruption mechanism is sequentially operated by a plurality of steps. The interruption mechanism improves the performance of the execution processing unit (1).

公开(公告)号：EP0223463A2

公开(公告)日：1987-05-27

申请号：EP86308468.7

申请日：1986-10-30

申请人： DATA GENERAL CORPORATION

发明人： Kerns, Daniel R. ,  Pilat, John F. ,  Gilgis, John r. ,  Kirkpatrick, Dana A.

IPC分类号： G06F9/46

CPC分类号： G06F9/4837 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/463

摘要： A multiple processor system in which a plurality of co-equal processors (11, 11A, 118, 11C share a common memory (12) which includes a data structure (13) for storing machine state information for a plurality of processing tasks (jobs) (14, 14A...). The instruction set of each of the processors includes a job processor instruction (JP FLUSH) for storing in the data structure the current machine state information (15) of a processing task being executed by a processor atthe time such execution has been stopped either because of an interruption thereof or because an allotted time period assigned to a processor for executing that task is over. The processor can then select another processing task and issue another instruction (JP LOAD) to obtain the machine state information therefor from the data structure (13) to permit such other task to be executed using this machine state information. A furhter instruction for permitting a faster load operation can also be issued by a processor when only a portion of the machine state information is required to be foaded. Other instructions are provided for various purposes useful in the multiple processor context.

摘要翻译： 一种多处理器系统，其中多个等同处理器（11,11A，11B，11C）共享公共存储器（12），该公共存储器包括用于存储用于多个处理任务（作业）的机器状态信息的数据结构（13） 14，14A ...）。 每个处理器的指令集包括作业处理器指令（JP FLUSH），用于在数据结构中存储处理任务的当前机器状态信息（15），处理任务在执行停止时由处理器执行，因为 或者由于分配给用于执行该任务的处理器的分配的时间段结束。 然后处理器可以选择另一个处理任务并发出另一个指令（JP LOAD），以从数据结构（13）获得机器状态信息，以允许使用该机器状态信息执行这样的其他任务。 当仅需要加载机器状态信息的一部分时，处理器也可以发出允许更快加载操作的更快的指令。 为在多处理器上下文中有用的各种目的提供了其他指令。

公开(公告)号：EP0220682A2

公开(公告)日：1987-05-06

申请号：EP86114722.1

申请日：1986-10-23

申请人： HITACHI, LTD.

发明人： Baba, Shiro

IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F9/34

CPC分类号： G06F9/30032 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/462 ,  G06F9/463

摘要： A data processing system has a data processing function to perform a data processing by specifying one of a plurality of register groups (BNO, BN1, BN2) according to an instruction. The instruction contains an information for indicating a change from a register group (BNO) to another register group (BN2) and an information for specifying desired one or two or more registers (R2, R15; R7, R12) in said register group(s). This enables to transfer the contents of the desired one or two or more registers to other registers at a register change.

摘要翻译： 数据处理系统具有通过根据指令指定多个寄存器组（BN0，BN1，BN2）中的一个来执行数据处理的功能。 指令包含用于指示从寄存器组（BN0）到另一寄存器组（BN2）的改变的信息和用于在所述寄存器组（BN2）中指定期望的一个或两个或更多个寄存器（R2，R15; R7，R12）的信息 ）。 这使得能够在寄存器改变时将期望的一个或两个或多个寄存器的内容传送到其他寄存器。

公开(公告)号：EP0104840A2

公开(公告)日：1984-04-04

申请号：EP83305408.3

申请日：1983-09-15

申请人： FUJITSU LIMITED

发明人： Kato, Motokazu ,  Matsumoto, Toshio

IPC分类号： G06F9/44 ,  G06F9/46

CPC分类号： G06F9/463 ,  G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1466 ,  G06F15/16

摘要： A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units (CPU 0 to CPU 3) and a main memory (5) to be commonly occupied by all the central processing units. The main memory is composed of an operating system area (3) and a firmware area (6). The firmware area is divided into a common firmware area (5) utilised by all the central processing units and a plurality of independent prefix areas (7-0 to 7-3) allotted to the central processing units (CPU 0 to CPU 3), Each prefix area is operative as an interface port, for a central processing unit, between the operating system area and the common firmware area.

摘要翻译： 包括固件的多处理器系统，该系统由至少多个中央处理单元和由所有中央处理单元共同占用的主存储器组成。 主存储器由操作系统区域和固件区域组成。 固件区域被分为由所有中央处理单元使用的公共固件区域和分配给中央处理单元的多个独立前缀区域。 每个前缀区域对于相应的中央处理单元在操作系统区域和公共固件区域之间用作接口端口。

公开(公告)号：EP0097258A2

公开(公告)日：1984-01-04

申请号：EP83105178.4

申请日：1983-05-25

申请人： International Business Machines Corporation

发明人： Reinsch, Roger Alan

IPC分类号： G06F9/46

CPC分类号： G06F9/468 ,  G06F9/463 ,  G06F11/1474 ,  G06F17/30 ,  G06F2201/80

摘要： Apparatus and method for operating a computing system to enable multiple users executing in various address spaces and according to various priorities, key states, and allocation levels to share the computing and data resources of the system. The computing system includes at least one subsystem (70) having a pool of available functional modules for supporting a plurality of user requests (81, 82, 85) under various access protocols (65-67) and allocation levels. Execution means are provided for assuring that user requests valid only under some protocols and allocation levels are not executed on behalf of users authorized only for different protocols, such execution means including means for generating an allocation descriptor describing a user's functional capability; means responsive to a request from a user which does not imply a change in functional capability for allocating a functional module to the user according to the user's currently allocated functional capability; and means responsive to a request from a user which implies a change in the user's functional capability for allocating a functional module to the user according to a new functional capability only if allower by the user's current functional capability.

摘要翻译： 用于操作计算系统以使多个用户能够在各种地址空间中执行并根据各种优先级，关键状态和分配级别来共享系统的计算和数据资源的装置和方法。 计算系统包括至少一个子系统（70），其具有用于在各种接入协议（65-67）和分配级别下支持多个用户请求（81,82,85）的可用功能模块池。 提供执行手段以确保用户请求仅在一些协议下有效，并且代表仅为不同协议授权的用户执行分配级别，这种执行装置包括用于生成描述用户功能能力的分配描述符的装置; 响应于来自用户的请求的装置，其不意味着根据用户当前分配的功能能力向用户分配功能模块的功能能力的改变; 以及响应于来自用户的请求的装置，其意味着只有当用户的当前功能能力允许时，这意味着用户的功能能力的改变才能根据新的功能能力向用户分配功能模块。

公开(公告)号：EP0097234A2

公开(公告)日：1984-01-04

申请号：EP83104281.7

申请日：1983-05-02

申请人： International Business Machines Corporation

发明人： Jenner, Earle Henderson

IPC分类号： G06F9/46

CPC分类号： G06F17/30 ,  G06F9/463 ,  G06F11/1441

摘要： A programming metnoa and structure for operating a computing system to restart a total subsystem or a subset of that subsystem to an operable state following a total interruption (system failure or termination, either normal or abnormal). The subsystem isolates inoperable resources while permitting the others to resume by independently maintaining in a first structure 90 the completion state 116, 120 of a resource manager's recovery responsibility with respect to each interrupted work unit and in a second structure 70 the operational states 82 and recovery log interest scopes 84, 86 of each resource manager. The completion state can be influenced by the starting or not of a resource manager, and if restarted, the presence or absence of a resource subset required to accomplish the work unit recovery.

公开(公告)号：EP0026589A2

公开(公告)日：1981-04-08

申请号：EP80303123.6

申请日：1980-09-05

申请人： PLESSEY OVERSEAS LIMITED

发明人： Wheatley, Nigel John ,  Andrews, Martyn Phillip

IPC分类号： G06F9/46

CPC分类号： G06F12/1483 ,  G06F9/463

摘要： Each process in a multi-process computing system using so-called capabilities may have associated with it a process dumpstack protected by the capability mechanism. The functions of this dumpstack are (i) to provide the state of the process at the point at which it was suspended and (ii) to stack (or nest) information relating to the invoked procedures (i.e. sub-routines) of the process. Thus there is a fixed sized portion containing principally the machine registers, the indicators and the watchdog timer values and a variable sized portion containing information related to each nested procedure. Each stack link is of fixed size and contains three items:- relativised instruction address, the code block capability and process capability pointer list block capability. This arrangement is enhanced to allowtwo additional classes of information to be stored in each link namely (a) an indication of the data and capability registers preserved during the domain change procedure and (b) descriptors for local storage segments. The use of descriptors for local storage allows a pool of storage particular to the process to be allocated on a segmented basis with the security of the capability mechanism extended into that local storage area. The descriptors for local storage segments resemble closely SCT entries (i.e. they contain sumcheck, base and limit values) and they are relative to a new protected stack, the local store stack, which is referenced by a hidden capability register C(L). The processor module is provided with a new instruction "subset local store" for use in local store segment allocation and automatic de-allocation occurs when a return is made from the procedure in which the local segment was allocated. Such allocation and de-allocation mechanisms use the indications which takes the form of a primary descriptor held in the most significant eight bits of the IAR word. This descriptor is allocated as follows:- (i) zero, no stacked registers or local segments allocated, (ii) m.s.b. = 1, stacked registers to be passed and (iii) I.s.b. 1-7 = 1, indicates the number of local store segments allocated. Associated with the stacked register set is a one word descriptor which indicates the registers stacked.

摘要翻译： 使用所谓功能的多进程计算系统中的每个进程可能与其相关联的是由能力机制保护的进程转储堆栈。 这个转储堆栈的功能是（i）提供进程挂起状态，以及（ii）堆栈（或嵌套）与进程的调用过程（即子程序）有关的信息。 因此，存在主要包括机器寄存器，指示器和看门狗定时器值的固定大小部分，以及包含与每个嵌套过程相关的信息的可变大小部分。 每个堆栈链路具有固定大小，包含三个项目：相对指令地址，代码块能力和进程能力指针列表块功能。 这种安排被增强以允许在每个链路中存储两个附加类别的信息，即（a）在域改变过程期间保留的数据和能力寄存器的指示，以及（b）本地存储段的描述符。 对本地存储的描述符的使用允许特定于进程的存储池以分段的方式分配。