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47 条记录 (耗时 0.009 秒)

    Rectifying transfer gate circuit
    21.
    发明公开
    Rectifying transfer gate circuit 失效
    整流传送门电路。

    公开(公告)号：EP0605253A3

    公开(公告)日：1995-03-01

    申请号：EP93310618.9

    申请日：1993-12-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Nakashima, Takashi

    IPC分类号： H03K19/094 ,  G06F7/50

    CPC分类号： G06F7/501 ,  G06F2207/3876 ,  H01L27/0727 ,  H03K19/09441 ,  H03K19/215

    摘要： A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

    Logic circuit
    24.
    发明公开
    Logic circuit 失效
    Logikschaltung。

    公开(公告)号：EP0055570A2

    公开(公告)日：1982-07-07

    申请号：EP81305982.1

    申请日：1981-12-21

    申请人： FUJITSU LIMITED

    发明人： Nishiuchi, Koichi

    IPC分类号： H03K19/017 ,  H03K19/003 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H03K19/09445 ,  H03K19/01721 ,  H03K19/09441

    摘要： A logic circuit has a first logic gate (G 6 ), having a plurality of inputs (a and b) and an output (m), and a second logic gate comprising a driving FET (Q 6 ) and a plurality of load FET's (T 6 ' and T 6 ). The gate of the driving FET (Q 6 ) is connected to the output (m) of the first logic gate and the gates of the load FET's (T 6 ' and T s ) are connected to respective inputs (a, b) of the first logic gate. The driving FET and the load FET's are connected in series.
    A pair of FET's (T', T), one depletion-mode and one enhancement-mode, with their drains, sources and gates respectively connected in common may be used in place of a single load FET.

    摘要翻译： 包括多输入NOR门，多个负载场效应晶体管（FET）和驱动FET的逻辑电路，负载FET和驱动FET在电源之间彼此串联连接，逻辑输出源自 负载FET和驱动FET的连接点。 NOR门的输入与负载FET的输入相同。 NOR门的输入端连接到负载FET的相应栅极，NOR门的输出端连接到驱动FET的栅极。

    Active loads, especially for use in inverter circuits
    27.
    发明公开
    Active loads, especially for use in inverter circuits 审中-公开
    Wechselrichterkreisen的Aktive Ladungen insbesondere zur Verwendung

    公开(公告)号：EP2768141A1

    公开(公告)日：2014-08-20

    申请号：EP13155542.7

    申请日：2013-02-15

    申请人： Technische Universität Darmstadt

    发明人： Ganesan, Ramkumar ,  Glesner, Prof. Dr. Manfred

    IPC分类号： H03K19/0944

    CPC分类号： H03K19/09441

    摘要： The invention relates to actives loads, especially for, but not limited to use in inverter circuits. The proposed active load comprises two transistors connected in an inventive way. The transistors may be PMOS or NMOS-organic transistors or transistors based on conventional silicon technologies or others.

    摘要翻译： 本发明涉及活性物质负载，特别是用于但不限于在逆变器电路中使用。 所提出的有源负载包括以本发明方式连接的两个晶体管。 晶体管可以是基于常规硅技术的其它PMOS或NMOS-有机晶体管或晶体管。

    Rectifying transfer gate circuit
    30.
    发明公开
    Rectifying transfer gate circuit 失效
    整流传输门电路

    公开(公告)号：EP0909033A3

    公开(公告)日：1999-10-20

    申请号：EP98203709.5

    申请日：1993-12-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Makashima, Takashi

    IPC分类号： H03K19/094

    CPC分类号： G06F7/501 ,  G06F2207/3876 ,  H01L27/0727 ,  H03K19/09441 ,  H03K19/215

    摘要： A rectifying transfer gate circuit includes first and second field effect transistors and one diode. The source of the first field effect transistor is coupled to a first input node and the gate thereof is coupled to a second input node. Meanwhile, the source of the second field effect transistor is coupled to the second input node and the gate thereof is coupled to the first input node. The diode is coupled between the common drain of the first and second field effect transistors and an output node, so as to increase the speed of the operation in the application circuit utilizing the above rectifying transfer gate circuit.

    摘要翻译： 整流传输门电路包括第一和第二场效应晶体管以及一个二极管。 第一场效应晶体管的源极耦合到第一输入节点并且其栅极耦合到第二输入节点。 同时，第二场效应晶体管的源极耦合到第二输入节点并且其栅极耦合到第一输入节点。 二极管耦接于第一及第二场效晶体管的公共漏极与输出节点之间，以利用上述整流传输门电路来提高应用电路的运作速度。