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53 条记录 (耗时 0.018 秒)

    PULSE SHAPER
    21.
    发明公开
    PULSE SHAPER 审中-公开

    公开(公告)号：EP3385756A1

    公开(公告)日：2018-10-10

    申请号：EP17165169.8

    申请日：2017-04-06

    申请人： Koninklijke Philips N.V.

    发明人： STEADMAN BOOKER, Roger ,  HERRMANN, Christoph

    IPC分类号： G01T1/24

    CPC分类号： G01T1/247 ,  H03K5/06 ,  H03K5/1532 ,  H03K2005/00065

    摘要： The invention relates to a pulse shaper (18). The pulse shaper (18) comprises an integrator (19) for generating a pulse having a peak amplitude indicative of the energy of a detected photon, a feedback resistor (22), switchable discharge circuitry (23) for discharging the integrator (19), and a peak detector (24) for detecting the peak of the pulse. The pulse shaper is adapted to start the discharge of the integrator by the switchable discharge circuitry based on the detection of the peak and to connect the feedback resistor in parallel to the integrator during a period of the pulse generation and to disconnect the feedback resistor during another period of the pulse generation. The pulse shaper can be such that the generation of the pulse is substantially unhindered by any noticeable concurrent discharging mechanism while, at the same time, the occurrence of energy pedestals can be efficiently avoided.

    Clock controlling method and circuit
    23.
    发明公开
    Clock controlling method and circuit 有权
    方法和电路，用于定时

    公开(公告)号：EP1189348A3

    公开(公告)日：2006-03-15

    申请号：EP01250273.8

    申请日：2001-07-20

    申请人： NEC Electronics Corporation

    发明人： Saeki, Takanori

    IPC分类号： H03K5/14 ,  H04L7/033

    CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

    摘要： A clock control circuit comprises a control circuit (102) for outputting a control signal for adding or subtracting a phase to or from a reference lock, respectively, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit(101) fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

    Balanced programmable delay element
    24.
    发明公开
    Balanced programmable delay element 审中-公开
    Programmierbares balanciertesVerzögerungsglied

    公开(公告)号：EP1408611A2

    公开(公告)日：2004-04-14

    申请号：EP03012818.5

    申请日：2003-06-05

    申请人： Agilent Technologies Inc. (a Delaware Corporation)

    发明人： Tang, Huajun

    IPC分类号： H03K5/13

    CPC分类号： H03K5/133 ,  H03K2005/00065 ,  H03L7/0814

    摘要： A balanced programmable delay element (300) that has a variable incremental delay. A first inverter (310) is provided that has a first electrode for receiving an input signal, a second electrode, a third electrode, and a fourth electrode for providing an output signal. The second electrode and the third electrode form a first current path, and the first inverter has a propagation delay that is dependent on the current through the first current path. A second inverter (320) is provided that has a first electrode coupled to the fourth electrode of the first inverter for receiving the output signal of the first inverter, a second electrode, a third electrode, and a fourth electrode for providing an output signal. The second electrode and the third electrode form a second current path, and the second inverter has a propagation delay that is dependent on the current through the second current path. A current switch (330) is coupled to the second electrode of the first inverter, the second electrode of the second inverter, the third electrode of the first inverter, and the third electrode of the second inverter. The current switch (330) receives at least two control signals, and responsive thereto, controls the amount of current through the first current path and the second current path, thereby selectively varying the incremental delay of the delay element.

    摘要翻译： 延迟单元具有一对具有四个电极和传播延迟的逆变器（310,320）。 传播延迟取决于通过电流路径的电流。 电流开关耦合到一个反相器的一对电极，另一个反相器的另一对电极。 电流开关接收两个控制信号，并响应于控制通过电流路径的电流量。

    Clock controlling method and circuit
    26.
    发明公开
    Clock controlling method and circuit 有权
    Verfahren und Schaltung zur Taktsteuerung

    公开(公告)号：EP1189348A2

    公开(公告)日：2002-03-20

    申请号：EP01250273.8

    申请日：2001-07-20

    申请人： NEC CORPORATION

    发明人： Saeki, Takanori

    IPC分类号： H03K5/14

    CPC分类号： H03L7/00 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071

    摘要： A clock control circuit comprises a control circuit (102) for outputting a control signal for adding or subtracting a phase to or from a reference lock, respectively, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit(101) fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

    摘要翻译： 一个时钟控制电路包括一个控制电路（102），用于在每个时钟周期内分别输出一个控制信号，该控制信号分别作为一个输入时钟或从该输入时钟生成的一个时钟的参考锁相加或相减 参考时钟和馈送有输入时钟的相位调整电路（101），并输出具有调整到参考时钟的相位的输出时钟。

    Delay circuit for ring oscillator with power supply noise compensation
    27.
    发明公开
    Delay circuit for ring oscillator with power supply noise compensation 有权
    具有电源噪声补偿的环形振荡器的延迟电路

    公开(公告)号：EP1178610A2

    公开(公告)日：2002-02-06

    申请号：EP01402082.0

    申请日：2001-08-01

    申请人： SONY CORPORATION

    发明人： Tachimori, Hiroshi, c/o Sony LSI Design Corp

    IPC分类号： H03L7/099 ,  H03K3/011 ,  H03K3/0231

    CPC分类号： H03K3/013 ,  H03K3/0315 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03K2005/00195 ,  H03K2005/00202 ,  H03L7/0812 ,  H03L7/0893 ,  H03L7/0995

    摘要： An inverter type delay circuit, voltage-controlled oscillation circuit, and voltage-controlled delay circuit capable of realizing simplification of circuit configuration, reduction of an effect of power source noise, and reduction of jitter, wherein a delay circuit (100), voltage-controlled oscillation circuit, and voltage-controlled delay circuit comprised of a plurality of delay stages controlled in drive current in accordance with a bias voltage or a control voltage (Vcnt1, ..., Vcntj) and determined in delay time by the drive current, adding a change (ΔVdd) of a power source voltage (Vdd) to the above bias voltage or control voltage (Vcnt1, ..., Vcntj) by a predetermined ratio (kc1, ..., kcj) and supplying a result of the addition (Vc1, ... Vcj) to the above delay stages to suppress the power source voltage dependencies of the delay times of the delay stages, or connecting by a predetermined ratio a plurality of delay stages having different power source voltage dependencies, for example, power source voltage dependencies of opposite delay times, to suppress the power source voltage dependencies of delay times of the delay stages are realized.

    摘要翻译： 本发明提供一种能够实现电路结构的简单化，电源噪声的影响的降低以及抖动的降低的反相器型延迟电路，电压控制振荡电路以及电压控制延迟电路，其中，延迟电路（100） 受控振荡电路和由控制驱动电流的多个延迟级构成的电压控制延迟电路，所述多个延迟级根据偏置电压或控制电压（Vcnt1，...，Vcntj）在驱动电流的延迟时间内被确定， 将电源电压（Vdd）的变化（ΔVdd）加上上述偏置电压或控制电压（Vcnt1，...，Vcntj）预定的比率（kc1，...，kcj），并提供 （Vc1，... Vcj）加到上述延迟级以抑制延迟级的延迟时间的电源电压依赖性，或者以预定比率连接具有不同电源电压依赖性的多个延迟级， 例如实现相反延迟时间的电源电压依赖性，以抑制延迟级的延迟时间的电源电压依赖性。

    Jitter absorption circuit
    30.
    发明公开
    Jitter absorption circuit 失效
    Absorptionsschaltung des Zitterns。

    公开(公告)号：EP0390226A1

    公开(公告)日：1990-10-03

    申请号：EP90108904.5

    申请日：1985-07-30

    申请人： YAMAHA CORPORATION

    发明人： Tomisawa, Norio

    IPC分类号： G11B20/10 ,  G11B20/22 ,  H04N9/89 ,  H04N5/95

    CPC分类号： H03K5/133 ,  G11B20/10009 ,  G11B20/225 ,  H03H11/265 ,  H03K3/0315 ,  H03K7/06 ,  H03K7/08 ,  H03K2005/00065 ,  H03K2005/00097 ,  H03K2005/00143 ,  H03K2005/00195

    摘要： A jitter absorption circuit comprises a variable delay device using CMOS gate circuit means for delaying the reproduced signal of a compact disc and a circuit (200,202,203,204,207) for reproducing time axis data of said reproduced signal. The delay time in said signal delay device (184) is controlled by an output signal of said time axis data reproducing circuit in such a manner that the delay time is prolonged when the reproduced signal is ahead of a reference position in the time axis direction and the delay time is shortened when the reproduced signal is delayed from the reference position whereby jitter in the reproduced signal is absorbed.

    摘要翻译： 抖动吸收电路包括使用用于延迟光盘的再现信号的CMOS门电路装置的可变延迟装置和用于再现所述再现信号的时间轴数据的电路（200,202,203,204,207）。 所述信号延迟装置（184）中的延迟时间由所述时间轴数据再现电路的输出信号控制，使得当再现信号在时间轴方向上超过基准位置时延迟时间延长，并且 当再现信号从参考位置延迟时，延迟时间缩短，从而吸收再现信号中的抖动。