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公开(公告)号：EP1791261A2
公开(公告)日：2007-05-30
申请号：EP07101761.0
申请日：1996-11-18
申请人： Fujitsu Ltd.
CPC分类号： H03L7/23 , H03L7/099 , H03L7/0995 , H03L7/0997 , H04L7/033
摘要： A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The retiming means (30A) comprises:
- a pulse generating circuit (306) detecting a level transition of said input data and generating a detected pulse (306a) having a pulse width δt to be provided to said unit circuit (20);
- a delay circuit (307) delaying said input data by a given delay time determined based on said pulse width δt in order to provide delayed data (307a); and
- a retiming circuit (308) carrying out a retiming operation for said delayed data (307a) by one of a leading edge and a trailing edge of said synchronized oscillation signal (203a) in order to generate said recovery data.摘要翻译： 一种半导体集成电路（30），包括构成锁相环的至少一部分并作为时钟恢复电路工作以产生基于输入数据的同步振荡信号的单元电路（20）和重定时装置（30A） 它通过来自所述输入数据的所述振荡输出信号产生恢复数据。 再定时部件（30A）包括： - 脉冲产生电路（306），用于检测所述输入数据的电平转换并产生具有要提供给所述单元电路（20）的脉冲宽度δt的检测脉冲（306a）; - 延迟电路（307），将所述输入数据延迟基于所述脉冲宽度δt确定的给定延迟时间，以便提供延迟数据（307a）; 以及 - 重定时电路（308），用于通过所述同步振荡信号（203a）的前沿和后沿中的一个对所述延迟数据（307a）执行重定时操作，以便产生所述恢复数据。
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公开(公告)号：EP1606883A1
公开(公告)日：2005-12-21
申请号：EP04719268.7
申请日：2004-03-10
申请人： Intel Corporation
发明人： SHAH, Prasanna , POISNER, David
IPC分类号： H03L7/099
CPC分类号： H03L7/0997 , H03L7/085
摘要： In some embodiments, a circuit includes an oscillator circuit (102)and a control circuit (104). The oscillator circuit generates a clock signal and includes a selectable delay circuit (106). The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating a selectable delay circuit in the oscillator circuit, in response to the control signal.
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公开(公告)号：EP1565989A1
公开(公告)日：2005-08-24
申请号：EP03774947.0
申请日：2003-10-28
IPC分类号： H03L7/081
CPC分类号： G11C29/028 , G01R31/31725 , G06F1/04 , G11C29/02 , G11C29/50012 , H03L7/0805 , H03L7/0812 , H03L7/0997
摘要： A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.
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24.发明授权
公开(公告)号：EP0657796B1
公开(公告)日：2005-03-02
申请号：EP94119499.5
申请日：1994-12-09
发明人： Ziegler, Horst , Diewald, Horst , Prexl, Franz , Bayer, Erich
CPC分类号： G06F1/08 , H03K5/135 , H03L7/089 , H03L7/0995 , H03L7/0997
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公开(公告)号：EP1406389A1
公开(公告)日：2004-04-07
申请号：EP03078675.0
申请日：1998-01-19
发明人： Kiyose, Masashi , Ito, Hiroya
CPC分类号： H03L7/0997 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/10 , H03L7/107 , H04N9/45 , H04N11/146
摘要： A phase locked loop (PLL) circuit (50) for generating an oscillation clock which maintains a substantially constant phase difference with respect to a phase of a reference clock, comprises:
a voltage controlled oscillator (107) receiving a control voltage and producing an oscillation clock having a frequency corresponding to the control voltage;
a comparison circuit (12) receiving the reference clock and the oscillation clock and comparing phases of the reference clock and the oscillation clock with each other to produce a comparison signal indicative of a comparison result;
a first charge pump circuit (51), connected to said comparison circuit, a ground potential and a power supply potential, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the first charge pump circuit pulls a constant current to ground from an output terminal of the first charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the first charge pump circuit when the power supply potential is selected, thereby producing a first output which alternately repeats the ground potential and the power supply potential;
a second charge pump circuit (52), connected to the comparison circuit, a ground potential and a power supply potential and having a drive performance with a higher output load than the first charge pump circuit, for receiving the comparison signal, and selecting one of the ground potential and the power supply potential in response to the comparison signal, wherein the second charge pump circuit pulls a constant current to ground from an output terminal of the second charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the second charge pump circuit when the power supply potential is selected, thereby producing a second output which alternately repeats the ground potential and the power supply potential;
a low-pass filter (30), connected between said first and second charge pump circuits and said voltage controlled oscillator, for smoothing one of the first and second outputs of the first and second charge pump circuits to produce the control voltage;
a lock detector (62) receiving the reference clock and the oscillation clock, detecting if the oscillation clock maintains a substantially constant phase difference with respect to the phase of the reference clock and producing a detection signal indicative of a detection result; and
a selecting circuit (63), connected to said first and second charge pump circuits and responsive to the detection signal, for operating said first charge pump circuit when the oscillation clock maintains the substantially constant phase difference with respect to the phase of the reference clock and operating said second charge pump circuit when the oscillation clock does not maintain the substantially constant phase difference with respect to the phase of the reference clock.-
公开(公告)号：EP0528283B1
公开(公告)日：1999-05-06
申请号：EP92113445.8
申请日：1992-08-06
申请人： SONY CORPORATION
发明人： Chiaki, Takano
CPC分类号： H03L7/0997 , G06F1/08 , H03K3/0315 , H03L7/089 , H03L7/183
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27.发明公开
公开(公告)号：EP0855802A2
公开(公告)日：1998-07-29
申请号：EP98300353.4
申请日：1998-01-19
发明人： Kiyose, Masashi , Ito, Hiroya
CPC分类号： H03L7/0997 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/10 , H03L7/107 , H04N9/45 , H04N11/146
摘要： A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation clock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.
摘要翻译： 输出与参考时钟同步的振荡时钟信号的PLL电路包括用于检测振荡时钟信号是否与参考时钟同步的锁相检测器。 如果锁相检测器检测到振荡时钟信号和参考时钟之间的相位差，则使用电荷泵电路来改变振荡时钟信号，使振荡信号与参考时钟同步。 响应于振荡时钟信号和参考时钟的比较结果，电荷泵选择接地电位和电源电位之一。 当选择接地电位时，电荷泵从电荷泵电路的输出端引出恒定的电流，并在选择电源电位时向电荷泵电路的输出端提供恒定电流，从而产生输出 其交替地重复地电位和电源电位。
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公开(公告)号：EP0528283A3
公开(公告)日：1993-07-07
申请号：EP92113445.8
申请日：1992-08-06
申请人： SONY CORPORATION
发明人： Chiaki, Takano
CPC分类号： H03L7/0997 , G06F1/08 , H03K3/0315 , H03L7/089 , H03L7/183
摘要： A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator (20), a divider (14), a phase comparator (15), and an up-down counter (16). The ring oscillator (20) provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider (14) divides the oscillation frequency from the ring oscillator (20) by a specified number. The phase comparator (15) compares the frequency of the signal from the divider (14) with the frequency of the external clock signal (S fe ). The up-down counter (16) controls the oscillation frequency of the ring oscillator (20) based on the comparison result from the comparator (15). The clock generator is controlled by an external clock signal (S fe ) to generate an Internal clock signal (S fc ) having a higher frequency and outputs both signals. By use of a digital integrated circuit technology alone, it becomes possible to include slow operating semiconductor elments and fast operating semiconductor elements on the same circuit chip without sacrificing the excellent characteristics of the latter.
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