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    METHOD AND APPARATUS FOR AUTOMATICALLY COMPENSATING A SPREAD SPECTRUM CLOCK GENERATOR
    24.
    发明授权
    METHOD AND APPARATUS FOR AUTOMATICALLY COMPENSATING A SPREAD SPECTRUM CLOCK GENERATOR 有权
    设备进行自动补偿蔓延-TAKTGENERATORS和程序

    公开(公告)号：EP1212829B1

    公开(公告)日：2005-06-22

    申请号：EP00959767.5

    申请日：2000-08-31

    Applicant: Lexmark International, Inc.

    Inventor： HARDIN, Bryan, Keith ,  HADADY, Craig, Eric

    IPC: H03D3/24 ,  H03L7/089 ,  H03L7/093 ,  H03L7/197 ,  H04B15/04

    CPC classification number: H04B15/04 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

    Abstract: An improved spread spectrum clock generator circuit is provided which automatically compensates for variations in passive component values and system gain and charge pump current in a Phase Locked Loop (PLL) circuit (100). The pulse widths of the UP (124) and DOWN (126) outputs of the Phase Frequency Detector (PFD) (122) are monitored at particular intervals to determine the deviation error of these UP and DOWN signals (124, 126), as compared to typical or nominal pulse-width durations. After an error is determined in the actual values of the pulse-width durations, the PLL system (100) is adjusted depending upon the magnitude and direction of the error signal. Changes in the PLL gain parameters, especially the VCO (134) gain and charge pump current, have a significant effect on the PFD (122) outputs, such that the width of the UP and DOWN signals (124, 126) vary as the frequency changes along the spread spectrum profile.

    Digital modulated signal receiver
    26.
    发明公开
    Digital modulated signal receiver 失效
    接收器，用于数字调制信号

    公开(公告)号：EP0831595A3

    公开(公告)日：2003-03-19

    申请号：EP97116190.6

    申请日：1997-09-17

    Applicant: NEC CORPORATION

    Inventor： Higuchi, Norihiko

    IPC: H04B1/16 ,  H04B15/04

    CPC classification number: H04L27/14 ,  H04B1/16 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/066 ,  H04L7/033

    Abstract: A radio receiver receives a 4-FSK signal through a radio system (101) and a detector (102) detects a four-level detected signal from the 4-FSK signal. The four-level detected signal is converted into digital form by an AD converter (104). The digital signal is stored onto a memory (114). The AD conversion is performed at intervals obtained from the four-level detected signal. A CPU (112) performs the data processing of the received digital data when the AD conversion is not performed and does not perform it when the AD conversion is performed.

    ZERO-DELAY BUFFER CIRCUIT FOR A SPREAD SPECTRUM CLOCK SYSTEM AND METHOD THEREFOR
    27.
    发明公开
    ZERO-DELAY BUFFER CIRCUIT FOR A SPREAD SPECTRUM CLOCK SYSTEM AND METHOD THEREFOR 审中-公开
    缓冲电路无延时一SPREIZSPEKTRUMSTAKTSYSTEM及相应方法

    公开(公告)号：EP1238461A1

    公开(公告)日：2002-09-11

    申请号：EP00978095.8

    申请日：2000-11-11

    Applicant: Neomicros Inc.

    Inventor： PARK, Joonbae

    IPC: H03L7/00 ,  G06F1/04

    CPC classification number: H03L7/0805 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/23 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067

    Abstract: A clock recovery circuit and a method for reduced electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generate an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

    Spread spectrum clock generator and associated method
    29.
    发明公开
    Spread spectrum clock generator and associated method 失效
    扩频时钟发生器及相关方法

    公开(公告)号：EP1073194A2

    公开(公告)日：2001-01-31

    申请号：EP00119532.0

    申请日：1994-11-29

    Applicant: Lexmark International, Inc.

    Inventor： Hardin, Keith B. ,  Fessler, John T. ,  Bush, Donald Reid ,  Booth, James Ronald

    IPC: H03C3/09

    CPC classification number: H03C3/0966 ,  H03B29/00 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/0805 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

    Abstract: A clock circuit includes an oscillator (15) for generating a reference frequency signal, and a spread spectrum clock generator (14) cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

    Abstract translation: 时钟电路包括用于产生参考频率信号的振荡器（15）以及与振荡器协作的扩频时钟发生器（14），用于产生扩频时钟输出信号，该扩频时钟输出信号具有基波频率和降低幅度的EMI频谱分量， 基本频率。 扩频时钟发生器最好包括一个用于产生一系列时钟脉冲的时钟脉冲发生器和一个用于对时钟脉冲发生器进行频率调制的扩频调制器，以扩大和平坦否则由时钟脉冲发生器产生的EMI频谱成分的幅度 。 扩频调制器频率调制具有相对于轮廓周期的频率偏差的特定轮廓的时钟脉冲。 还公开了包括扩频时钟电路和相关方法的电子设备。

    Clock distribution via suppressed carrier to reduce EMI
    30.
    发明公开
    Clock distribution via suppressed carrier to reduce EMI 失效
    具有抑制载波的帮助下减少电磁干扰时钟分配

    公开(公告)号：EP0823801A3

    公开(公告)日：2000-06-21

    申请号：EP97305174.1

    申请日：1997-07-14

    Applicant: Hewlett-Packard Company

    Inventor： Arnett, David W.

    IPC: H04L7/00 ,  G06F1/04 ,  H04B15/04 ,  H04L25/02 ,  H04L25/08 ,  G06F1/10

    CPC classification number: G06F1/10 ,  H04B15/04 ,  H04B2215/064 ,  H04B2215/067 ,  H04L7/0083 ,  H04L27/04

    Abstract: In a computer or other digital system a clock or other synchronous signal (12) is routed from a source (16) to a destination (18) as a double side band suppressed carrier (DSB-SC) signal (14). The clock or other synchronous signal is amplitude modulated at the source using a broadband low frequency envelope signal (20). The modulated signal is the DSB-SC signal, which then is routed over PC board traces (15) to the destination. At the destination, the DSB-SC signal is demodulated to achieve the clock or other synchronous signal (60). The envelope signal (20,20') is separately generated from a common key (72) at both the source and destination, is routed to bother the source to the destination, or is routed from the source to the destination.

    Abstract translation: 在计算机或其他数字系统的时钟或其它同步信号（12）从源（16）到目的地（18）作为一个双边带抑制载波（DSB-SC）信号（14）进行路由。 时钟或其它同步信号是幅度调制的使用宽带低频包络线信号（20）在源。 经调制的信号是DSB-SC信号，该信号然后被路由通过PC板迹线（15）到目的地。 在目的地，所述DSB-SC信号进行解调，以实现时钟或其它同步信号（60）。 包络信号（20,20“）分别从在源和目的地的公共密钥（72）产生的，被路由到源打扰到目的地，或者从源到目的地路由。

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