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公开(公告)号：EP0540665A4
公开(公告)日：1993-06-23
申请号：EP91914944
申请日：1991-07-23
CPC分类号： G06F5/14 , G06F2205/102 , G11C7/22 , G11C8/06
摘要： A method and apparatus are disclosed for storing and accessing information of both asynchronous and synchronous devices using, for example, pointers (62, 76) having grey code counters which reduce code conversion logic and which are less susceptible to clock glitches, such as improper clock pulses due to internal circuit timing errors. Because the devices are less clock dependent, they do not require the imposition of critical paths during the placement and routing of a circuit layout. Further, fast and reliable accessing of information stored in memory devices can be achieved by multiplexing (80) output bits addressed, for example, via the aforementioned grey code pointers.
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公开(公告)号：EP0477293A1
公开(公告)日：1992-04-01
申请号：EP90910639.0
申请日：1990-06-11
IPC分类号： H03M1
CPC分类号： H03M1/0678 , H03M1/785
摘要： Un convertisseur numérique/analogique de multiplication comprend des pattes de dérivation, dans lesquelles un commutateur (15) comporte une borne commune connectée à un noeud respectif (12) dans le chemin en série ainsi que deux bornes commutables connectées chacune à une résistance respective. Chaque branche de la série se compose d'un commutateur fictif (28) en série avec une résistance intercalée (13) ayant la moitié de la valeur de résistance de chacune des résistances de dérivation (14', 14''). Les commutateurs, mis en oeuvre de préférence en technologie MOS complémentaire sont physiquement appareillés et les commutateurs se trouvant dans les branches sont configurés pour être fermés, de sorte que la résistance de chaque commutateur fictif représente la moitié de celle du commutateur se trouvant dans la patte de dérivation respective. L'agencement permet de conserver la relation R-2R entre la série et les résistances de dérivation, et améliore ainsi sensiblement la linéarité dudit convertisseur.
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公开(公告)号：EP0766424B1
公开(公告)日：2003-12-03
申请号：EP96306395.3
申请日：1996-09-04
发明人： Takahashi, Richard , Shea, Neil
IPC分类号： H04L9/00
CPC分类号： H04L9/088 , H04L2209/12
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公开(公告)号：EP0771490B1
公开(公告)日：2001-05-02
申请号：EP96914667.9
申请日：1996-05-16
IPC分类号： H03K3/0231 , H03L7/099
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages (132-140). The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN-terminal. The drain terminal of MOS transistor M4 provides an OUT- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.
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公开(公告)号：EP0813322A3
公开(公告)日：1999-11-24
申请号：EP97109490.9
申请日：1997-06-11
IPC分类号： H04L7/04
CPC分类号： H04L7/041 , H04J3/0685
摘要： The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.
摘要翻译： 异步定时发生器由产生主时钟信号的时钟信号发生器组成。 主时钟信号由主时钟计数器使用以产生位时钟。 主时钟计数器将主时钟信号的频率降低到较低的频率。 从数据流的时隙成帧提取控制信号信息，以控制对可变计数器的预定计数值的使用。 可变计数器使用该低频时钟信号来产生子位计数时钟信号和时隙位数。 响应于耦合到定时器的控制信号产生这些信号，指示用于在所接收的流中重新同步数据恢复的时隙的不同字段。 在优选实施例中，在通信收发器设备中使用异步定时发生器以允许接收的通信数据的重新同步。
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公开(公告)号：EP0885511A2
公开(公告)日：1998-12-23
申请号：EP97914891.0
申请日：1997-03-06
发明人： THOMAS, John, C.
CPC分类号： H04L27/2017 , H04L25/03834
摘要： A VCO modulator controller including a ROM memory storing a number of waveform maps, a counter coupled to the ROM memory and capable of developing a sequence of ROM addresses, a temporal bit generator responsive to a data stream to develop a next bit Nb, a current bit Cb, and a past bit Pb, control circuitry developing a digital waveform signal from selected waveform maps in the ROM memory using the Nb, Cb, and Pb bits and the sequence of ROM memory outputs, and a DAC that converts the digital waveform signal to an analog VCO control signal that encodes said data stream. A method for providing a modulated control voltage includes: (a) storing a number of waveform maps in a memory; (b) generating a number of temporal bits including a next bit Nb, a current bit Cb, and a past bit Pb from a data stream; (c) developing a series of addresses for the memory to create a sequence of digital outputs; (d) developing a digital waveform utilizing said Nb, Cb, and Pb bits and the sequence of digital outputs of said memory; and (e) converting said digital waveform signal to an analog VCO control signal that encodes said data stream.
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公开(公告)号：EP0695477A4
公开(公告)日：1998-10-14
申请号：EP94912748
申请日：1994-02-17
申请人： VLSI TECHNOLOGY INC
发明人： THOMAS STEVEN D
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , H03K19/0948 , H03K19/096 , H03K19/20
CPC分类号： G06F7/501 , H03K19/0963
摘要： The present invention relates to an implementation of domino logic using a logic cell (200, 300) which is not limited to the use of positive logic functions, and which can be implemented using MOS technology. A significant feature is the use of a single clock cycle (PHI1) to generate separate clock phases (PHI1, PHI1d) for a first function, such as the carry function of a full-adder logic cell, and a second function, such as the sum function in the full-adder logic cell. The separate clock phase for gating the second function corresponds to a delayed version of the clock phase used to gate the first function, wherein the clock delay corresponds to a delay through the first function. In one exemplary embodiment, the delay can be made equal to that of the first function by using circuitry identical to that of the first function to create the delay.
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公开(公告)号：EP0813322A2
公开(公告)日：1997-12-17
申请号：EP97109490.9
申请日：1997-06-11
IPC分类号： H04L7/04
CPC分类号： H04L7/041 , H04J3/0685
摘要： The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.
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39.发明公开METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN DIGITAL ELECTRONIC CIRCUITS 失效方法和设备，以降低功耗在数字电子电路
公开(公告)号：EP0809825A1
公开(公告)日：1997-12-03
申请号：EP96904627.0
申请日：1996-02-12
IPC分类号： G06F1
CPC分类号： G06F1/3287 , G06F1/3203 , Y02D10/171 , Y02D50/20
摘要： An integrated circuit with power conservation includes a number of functional blocks, each of which includes a digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.
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公开(公告)号：EP0771491A1
公开(公告)日：1997-05-07
申请号：EP96920258.0
申请日：1996-05-16
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.
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