公开(公告)号：EP3561872A1

公开(公告)日：2019-10-30

申请号：EP19162646.4

申请日：2019-03-13

申请人： eMemory Technology Inc.

发明人： Lai, Chih-Wei ,  Ting, Yun-Jen ,  Wu, Yi-Han ,  Lin, Kun-Hsin ,  Hsu, Hsin-Kun

IPC分类号： H01L27/02 ,  H02H9/04

摘要： An ESD circuit is connected to a power pad and a first node. The ESD circuit includes a RC circuit and a first ESD current path. The RC circuit is connected between the power pad and the first node. The RC circuit is capable of providing a first control voltage and a second control voltage. The first ESD current path is connected between the power pad and the first node. When the power pad receives a positive ESD zap, the first ESD current path is turned on in response to the first control voltage and the second control voltages provided by the RC circuit, so that an ESD current flows from the power pad to the first node through the first ESD current path.

公开(公告)号：EP3389050B1

公开(公告)日：2019-10-09

申请号：EP17168476.4

申请日：2017-04-27

申请人： eMemory Technology Inc.

发明人： Wong, Wei-Zhe ,  Hsu, Ching-Hsiang ,  Yang, Ching-Sung

IPC分类号： G11C7/24 ,  G11C16/04 ,  G11C17/16 ,  H04L9/32

公开(公告)号：EP3454320A1

公开(公告)日：2019-03-13

申请号：EP18190627.2

申请日：2018-08-24

申请人： eMemory Technology Inc.

发明人： WU, Meng-Yi ,  CHEN, Hsin-Ming

IPC分类号： G09C1/00 ,  H04L9/08 ,  G06F21/86 ,  H04L9/32

摘要： A random code generator is installed in a semiconductor chip and includes a PUF cell array, a control circuit and a verification circuit. The PUF cell array includes m×n PUF cells. The control circuit is connected with the PUF cell array. While a enroll action is performed, the control circuit enrolls the PUF cell array. The verification circuit is connected with the PUF cell array. While a verification action is performed, the verification circuit determines that p PUF cells of the PUF cell array are normal PUF cells and generates a corresponding a mapping information, wherein p is smaller than m×n. While the semiconductor chip is enabled, the control circuit reads states of the p normal PUF cells of the PUF cell array according to the mapping information and generates a random code according to the states.

公开(公告)号：EP3232442B1

公开(公告)日：2019-01-30

申请号：EP17166177.0

申请日：2017-04-12

申请人： eMemory Technology Inc.

发明人： LI, Chun-Hsiao ,  CHEN, Wei-Ren ,  CHEN, Hsueh-Wei

IPC分类号： G11C16/04 ,  H01L27/11558 ,  G11C16/10

公开(公告)号：EP2398022B1

公开(公告)日：2018-11-21

申请号：EP11150942.8

申请日：2011-01-14

申请人： eMemory Technology Inc.

发明人： Ching, Wen-Hao ,  Wang, Shih-Chen ,  Yang, Ching-Sung

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory system includes one or more non-volatile memory cells (20, 40). Each non-volatile memory cell (20, 40) comprises a floating gate, a coupling device (300, 500), a first floating gate transistor (310, 510), and a second floating gate transistor (320, 520). The coupling device (300, 500) is located in a first conductivity region. The first floating gate transistor (310, 510) is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor (320, 520) is located in a third conductivity region. Such non-volatile memory cell (20, 40) further comprises two transistors (330, 340, 530, 540) for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor (320, 520) during an erase operation. The floating gate is shared by the first floating gate transistor (310, 510), the coupling device (300, 500), and the second floating gate transistor (320, 520), and extends over active regions of the first floating gate transistor (310, 510), the coupling device (300, 500) and the second floating gate transistor (320, 520).

公开(公告)号：EP3133609B1

公开(公告)日：2018-08-08

申请号：EP16183389.2

申请日：2016-08-09

申请人： eMemory Technology Inc.

发明人： WONG, Wei-Zhe ,  YANG, Ching-Sung ,  HSU, Ching-Hsiang

IPC分类号： G11C17/16 ,  G11C7/24

CPC分类号： G11C17/18 ,  G06F21/44 ,  G11C7/24 ,  G11C17/16

摘要： The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

公开(公告)号：EP3309836A1

公开(公告)日：2018-04-18

申请号：EP17162330.9

申请日：2017-03-22

申请人： eMemory Technology Inc.

发明人： TING, Yun-Jen ,  LAI, Chih-Wei ,  SHEN, Chiun-Chi ,  HSU, Hsin-Kun

IPC分类号： H01L27/02

CPC分类号： H02H9/046 ,  G11C17/16 ,  H04L9/3278

摘要： An ESD circuit is connected with a pad. The ESD circuit includes a P-type transistor, an N-type transistor and a control circuit. A first source/drain terminal of the P-type transistor is connected with the pad. A first source/drain terminal of the N-type transistor is connected with a second source/drain terminal of the P-type transistor. A second source/drain terminal of the N-type transistor is connected with a first node. The control circuit is connected with the pad, the first node, a gate terminal of the P-type transistor and a gate terminal of the N-type transistor. When the pad receives an ESD zap, the control circuit provides a first voltage drop to the P-type transistor and provides a second voltage drop to the N-type transistor, so that the P-type transistor and the N-type transistor are turned on.

摘要翻译： ESD电路连接到一个焊盘。 ESD电路包括P型晶体管，N型晶体管和控制电路。 P型晶体管的第一源极/漏极端子与焊盘连接。 N型晶体管的第一源极/漏极端子与P型晶体管的第二源极/漏极端子连接。 N型晶体管的第二源极/漏极端连接第一节点。 控制电路与焊盘，第一节点，P型晶体管的栅极端子和N型晶体管的栅极端子连接。 当所述焊盘接收到ESD消除时，所述控制电路向所述P型晶体管提供第一电压降，并向所述N型晶体管提供第二电压降，以使所述P型晶体管和所述N型晶体管导通 上。

公开(公告)号：EP3270498A1

公开(公告)日：2018-01-17

申请号：EP17152953.0

申请日：2017-01-25

申请人： eMemory Technology Inc.

发明人： Shao, Chi-Yi

IPC分类号： H02M3/07

CPC分类号： G11C5/145 ,  G11C16/0433 ,  G11C16/12 ,  H02M3/073 ,  H02M2001/007 ,  H03K3/0315 ,  H03K17/28 ,  H03K19/20

摘要： A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

摘要翻译： 提供了一种电荷泵装置。 根据环形振荡器电路的延迟电路之间的耦合节点的延迟信号产生用于分别驱动两相电荷泵电路和四相电荷泵电路的两相时钟信号和四相时钟信号。

公开(公告)号：EP3196886A1

公开(公告)日：2017-07-26

申请号：EP17152172.7

申请日：2017-01-19

申请人： eMemory Technology Inc.

发明人： Huang, Chih-Yang ,  Ku, Wei-Ming

IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C7/065 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11558 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42328

摘要： A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. An output signal is outputted from the node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. The first supply voltage, the second supply voltage or the bias voltage is selected as the output signal.

摘要翻译： 功率开关电路包括第一晶体管，第二晶体管和电流源。 第一晶体管的第一源极/漏极端子和栅极端子分别接收第一电源电压和第二电源电压。 第一晶体管的第二源极/漏极端子和体端子与节点z连接。 输出信号从节点z输出。 第二晶体管的第一源极/漏极端子和栅极端子分别接收第二电源电压和第一电源电压。 第二晶体管的第二源极/漏极端子和本体端子与节点z连接。 电流源连接在偏置电压和节点z之间。 选择第一电源电压，第二电源电压或偏置电压作为输出信号。

公开(公告)号：EP3157013A1

公开(公告)日：2017-04-19

申请号：EP15195161.3

申请日：2015-11-18

申请人： eMemory Technology Inc.

发明人： Chang, Wei-Chen ,  Ching, Wen-Hao ,  Chen, Chih-Hsin ,  Wang, Shih-Chen ,  Yang, Ching-Sung

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： A memory array (300) includes a first memory page (MP1) and a second memory page (MP2). The first memory page (MP1) includes a plurality of first memory cells (M1C 1 to M1C N ) each coupled to a first word line (WL 1 ), a first select gate line (SG 1 ), a first control line (CL 1 ), and a first erase line (EL 1 ), and for receiving a bit line signal (SBL 1 , SBL n , SBL N ) and a source line signal (SSL 1 , SSL n , SSL N ). The second memory page (MP2) includes a plurality of second memory cells (M2C 1 to M2C N ) each coupled to the first word line (WL 1 ), the first select gate line (SG 1 ), a second control line (CL 12 ), and a second erase line (EL 12 ), and for receiving a bit line signal (SBL 11 to SBL 1N ) and a source line signal (SSL 11 to SSL 1N ). By arranging memory cells in different memory pages, the flexibility of memory operations is achieved.

摘要翻译： 存储器阵列（300）包括第一存储器页（MP1）和第二存储器页（MP2）。 第一存储页（MP1）包括分别耦合到第一字线（WL 1），第一选择栅极线（SG1），第一控制线（CL1）的多个第一存储单元（M1C1至M1CN） ）和第一擦除线（EL1），并且用于接收位线信号（SBL 1，SBL n，SBL N）和源极线信号（SSL 1，SSL n，SSL N）。 第二存储器页（MP2）包括分别耦合到第一字线（WL 1），第一选择栅极线（SG1），第二控制线（CL12）的多个第二存储单元（M2C 1至M2C N） ）和第二擦除线（EL12），并且用于接收位线信号（SBL 11至SBL 1N）和源极线信号（SSL 11至SSL 1N）。 通过将存储单元布置在不同的存储器页面中，实现了存储器操作的灵活性。