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公开(公告)号：EP0440449A2
公开(公告)日：1991-08-07
申请号：EP91300722.5
申请日：1991-01-30
申请人： MOTOROLA, INC.
CPC分类号： H03C3/095 , H03C3/0933 , H03C2200/005 , H03C2200/0079 , H03C2200/0083 , H03L7/189
摘要： In a fast-switching frequency synthesizer switching between receiving and transmitting mode frequency is done by changing the divisor of the loop divider and by presteering voltage injection at the voltage controlled oscillator ("VCO") with feedback to allow the VCO, and synthesizer, to quickly transition between two given frequencies. This presteering mechanism, with the feedback, allows the presteering voltage to track the variations in the VCO gain from device to device, and gain changes while in operation. This same information is used to implement a means of automatically adjusting the FM deviation of the transmitter since that information varies with the gain of the VCO as does the FM deviation.
摘要翻译： 在快速切换频率合成器中，在接收和发射模式频率之间切换，通过改变环路分频器的除数，并通过反馈来预压力在压控振荡器（“VCO”）处进行电压注入，从而使VCO和合成器 在两个给定频率之间快速过渡。 通过反馈，这种预转向机制允许预导电压跟踪VCO设备中VCO增益的变化，并在运行时获得变化。 这种相同的信息用于实现自动调整发射机的FM偏差的手段，因为该信息随FM的增益而变化，与FM偏差一样。
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公开(公告)号：EP0360442A1
公开(公告)日：1990-03-28
申请号：EP89308858.3
申请日：1989-09-01
CPC分类号： H03L7/189 , H03L7/14 , H03L7/199 , H03L2207/05
摘要： The oscillation frequency of a voltage controlled oscillator (4) is controlled by setting a division ratio of a variable ratio divider (2) provided in a feedback path of a phase locked loop. When the frequency is switched by changing the division ration a steering voltage (Vda) is applied to the voltage controlled oscillator. This steering voltage can compensate non-linearity so as to reduce the frequency errors and phase errors after switching to thereby enable high speed frequency switching.
摘要翻译： 压控振荡器（4）的振荡频率通过设置设置在锁相环的反馈路径中的可变比分频器（2）的分频比来控制。 当通过改变分频来切换频率时，转向电压（Vda）被施加到压控振荡器。 该转向电压可以补偿非线性，以便在切换之后减少频率误差和相位误差，从而实现高速频率切换。
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33.发明公开
公开(公告)号：EP0315489A3
公开(公告)日：1989-07-19
申请号：EP88310430.9
申请日：1988-11-07
摘要： Signal generating apparatus comprises a phase-locked loop (PLL) (1,3,5,7,9) utilizing a voltage-controlled oscillator (VCO) (1) and a frequency-locked loop (FLL) (9,1,13) to generate an output signal, the frequency of which jumps from one value to another in a selectable sequence; the signal generator further includes a delay line discriminator (13) to provide an error signal to compensate for FM noise in the VCO (1). The frequency-locked loop is implemented by utilizing the FM error signal from the delay line discriminator (13) to stabilize the center frequency of the VCO (1). The inherent wide bandwidth of the FLL provides a fast settling time when the loop is switched to a new frequency. In a learn mode, the gain parameters of the loop are determined and stored for each of a plurality of frequencies. The gain parameters and a corresponding pretune signal for each selected frequencies are then applied to the FLL in a selectable sequence to provide a fast-switching signal generator.
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公开(公告)号：EP1547249B1
公开(公告)日：2011-04-20
申请号：EP03798305.3
申请日：2003-09-15
申请人： ST-Ericsson SA
发明人： CHARLON, Olivier
IPC分类号： H03L7/189
CPC分类号： H03L7/189
摘要： A frequency synthesizing circuit includes a voltage-controlled oscillator (40) whose frequency is preset to a value, and which generates an oscillating signal in response to an input voltage. A digital processing unit (60) can disable the circuit to operate in phase locked loop mode. Once the circuit is disabled, the unit determines a first and second frequency of the oscillating signal in response to respective first and second loop filter input voltage values. The unit further generates a control value from the two frequencies, the frequency divider dividing ratio and the reference signal. The circuit further comprises a D/A converter (70) configured to preset the loop filter input voltage to a preset value in response to the control value. Once the oscillator output oscillates at the corresponding input preset value, the unit (60) disables the D/A converter (70) and enables the frequency synthesizing to operate in phase locked loop mode.
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公开(公告)号：EP2119090A1
公开(公告)日：2009-11-18
申请号：EP08719521.0
申请日：2008-02-29
申请人： NXP B.V.
CPC分类号： H04L7/10 , H03L7/0891 , H03L7/10 , H03L7/189 , H04L7/04
摘要： A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.
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公开(公告)号：EP1976126A1
公开(公告)日：2008-10-01
申请号：EP07707488.8
申请日：2007-01-26
发明人： KITAYAMA, Yasuo c/o NIHON DEMPA KOGYO CO., LTD., , KIMURA, Hiroki c/o NIHON DEMPA KOGYO CO., LTD., , ONISHI, Naoki c/o NIHON DEMPA KOGYO CO., LTD., , TSUKAMOTO, Nobuo c/o DSP TECHNOLOGY AS.
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC (4) that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC (6) that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF (5) that removes noise from the output signal from the coarse adjustment DAC (4) and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF (7) that converts the output signal from the fine adjustment DAC (6) to a voltage, thereby smoothing the signal; a resistor (R6) that connects an input stage of the LPF (5) to that of the LPF (7); and a capacitor (C8) used for providing a capacitive coupling such that the output of the LPF (7) is added to that of the LPF (5).
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC（4）以输出模拟信号; 微调DAC（6），其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF（5），其从粗调DAC（4）的输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 将来自微调DAC（6）的输出信号转换成电压的高响应速度LPF（7），从而平滑信号; 连接LPF（5）的输入级与LPF（7）的输入级的电阻器（R6）; 以及用于提供电容耦合的电容器（C8），使得LPF（7）的输出被添加到LPF（5）的输出。
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公开(公告)号：EP1030452A3
公开(公告)日：2003-10-29
申请号：EP00103071.7
申请日：2000-02-15
发明人： Eckardt, Holger
摘要： Kommunikationseinrichtungen enthalten, beispielsweise in Dekodereinrichtungen und Frequenzerzeugungseinrichtungen, Oszillatoren, die häufig eine phasenverkoppelte Regelschleife (Phase-Locked Loop, PLL), d. h. einen Phasenregelkreis, enthalten. Das Signal des freischwingenden Oszillators ist dabei phasenstarr mit einem Referenzsignal gekoppelt. Um eine hohe Frequenzagilität zu erreichen, erfolgt in dem erfindungsgemäßen Phasenregelkreis (100: 300: 400) die Einstellung eines Ausgangssignals (111: 311: 411) mit einer gewünschten Frequenz zunächst in einem Steuerbetrieb und anschließend in einem Regelbetrieb. Die Umschaltung von dem Steuerbetrieb in den Regelbetrieb erfolgt, nachdem die Spannung eines ersten Steuersignals (113: 313: 413) und die Spannung eines zweiten Steuersignals (115, 118: 315, 318: 415, 418), innerhalb eines vorgegebenen Bereichs, gleich sind, so daß sich die Umschaltung nicht wesentlich auf das Signal am Eingang des spannungsgesteuerten Oszillators (101: 301: 401) auswirkt. Der erfindungsgemäße Phasenregelkreis (100: 300: 400) ermöglicht eine Frequenzerzeugung mit hoher Frequenzstabilität und Signalreinheit bei hoher Frequenzagilität.
摘要翻译： 通信设备包括例如解码器设备和频率发生器，振荡器通常使用锁相环（PLL），即， 小时。 一个锁相环。 自激式振荡器的信号被锁相耦合到参考信号。 为了实现高频敏捷性，在根据本发明的锁相环路（100：300：400）中，具有期望频率的输出信号（111：311：411）的设置首先在控制模式下然后在控制模式下进行。 （：313：113 413）的控制模式的切换为第一控制信号的电压之后控制动作和第二控制信号的电压（115，118：315，318：415，418）在预定范围内，是相同的 使得开关不会显着影响压控振荡器（101：301：401）输入端的信号。 （：300：400 100）提供的频率生成与在高频率捷变高的频率稳定度和信号完整性的相位根据本发明的锁定环。
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公开(公告)号：EP1223676A2
公开(公告)日：2002-07-17
申请号：EP01309826.4
申请日：2001-11-22
申请人： FUJITSU LIMITED
IPC分类号： H03L7/099
CPC分类号： H03L7/0805 , H03L1/022 , H03L7/0893 , H03L7/10 , H03L7/189
摘要： A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is opposite to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.
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39.发明公开Phase locked loop having a reduced lock time 有权Phasenregelschleife mit verringerter Verriegelungszeit
公开(公告)号：EP1182780A2
公开(公告)日：2002-02-27
申请号：EP01306946.3
申请日：2001-08-15
申请人： Tektronix, Inc.
发明人： Sutton, Brian P.
IPC分类号： H03L7/189
CPC分类号： H03L7/189 , H03L2207/06
摘要： A reduced lock time phase locked loop has a speed up circuit with an operational amplifier (24) to amplify a differential voltage across a filter resistor (R1) of an RC noise filter, the RC noise filter (R1,C) coupling a coarse tune voltage to a VCO (12). The amplified differential voltage is applied to the bases of a pair of opposite polarity transistors (Q1,Q2), the emitters of the transistors being coupled to a filter capacitor (C) in the RC noise filter for rapid charging/discharging.
Alternatively the amplified differential voltage is applied to a pair of parallel, opposite polarity diodes (D1,D2) coupled to the filter capacitor for rapid charging/discharging.摘要翻译： 缩短的锁定时间锁相环具有与运算放大器（24）的加速电路，以放大RC噪声滤波器的滤波电阻器（R1）两端的差分电压，RC噪声滤波器（R1，C）将粗调 电压到VCO（12）。 放大的差分电压施加到一对相反极性晶体管（Q1，Q2）的基极，晶体管的发射极耦合到用于快速充电/放电的RC噪声滤波器中的滤波电容器（C）。 或者，放大的差分电压被施加到耦合到滤波电容器的一对并联的相反极性二极管（D1，D2），用于快速充电/放电。
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40.发明公开PLL frequency synthesizer capable of changing an output frequency at a high speed 失效PLL频率合成器，其能够使输出的高速的频率变化
公开(公告)号：EP0840457A3
公开(公告)日：1999-08-25
申请号：EP97204136.2
申请日：1991-10-17
申请人： NEC Corporation
发明人： Norimatsu, Hidehiko
IPC分类号： H03L7/093
CPC分类号： H03L7/183 , H03L7/0898 , H03L7/107 , H03L7/146 , H03L7/18 , H03L7/189 , H03L7/1972
摘要： In a frequency synthesizer, a first pulse removing circuit (31) is connected between a reference signal generator (21) and a phase-frequency comparator (24). A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator. Responsive to first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit may control current supplied from/to a charge pump circuit (25). A control circuit may be connected between the phase-frequency comparator and the charge pump circuit. A switch may be inserted between the loop filter and the voltage controlled oscillator. When the switch switches off a PLL, a D/A converter supplies a control voltage to the voltage controlled oscillator and a filter capacitor of the loop filter. The charge pump circuit may comprise a control circuit, a constant current circuit, an integrating circuit, and a sample and hold circuit.
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