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公开(公告)号：EP0552601A3
公开(公告)日：1993-12-08
申请号：EP93100085.5
申请日：1993-01-05
CPC分类号： G01R25/08 , H03D13/001 , H03L7/091 , H03L7/183
摘要： A modulus counter (13B) counts first clock pulses (PCK1) to modulus M and ouputs the count value (Cm) as an m-bit reference signal (S R ), M being an integer. A latch circuit (14) samples and holds the reference signal in response to a trigger signal (Tr) generated by a trigger signal generator (17) in synchronism with an input signal (Sx). A high-speed counter (16) is supplied with second clock pulses (PCK2) of a frequency higher than that of the first clock pulses and starts counting the second clock pulses in response to the trigger signal and stops the counting in response to a first one of the first clock pulses immediately thereafter. A data processor (18) converts the n-bit count value (Cn) of the high-speed counter to n-bit data corresponding to a phase fraction of a phase quantization step in the latch, combines the n-bit data as low-order bits with m-bit data from the latch and outputs the combined data as phase difference data.
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公开(公告)号：EP0360442B1
公开(公告)日：1994-07-20
申请号：EP89308858.3
申请日：1989-09-01
CPC分类号： H03L7/189 , H03L7/14 , H03L7/199 , H03L2207/05
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公开(公告)号：EP0360442A1
公开(公告)日：1990-03-28
申请号：EP89308858.3
申请日：1989-09-01
CPC分类号： H03L7/189 , H03L7/14 , H03L7/199 , H03L2207/05
摘要： The oscillation frequency of a voltage controlled oscillator (4) is controlled by setting a division ratio of a variable ratio divider (2) provided in a feedback path of a phase locked loop. When the frequency is switched by changing the division ration a steering voltage (Vda) is applied to the voltage controlled oscillator. This steering voltage can compensate non-linearity so as to reduce the frequency errors and phase errors after switching to thereby enable high speed frequency switching.
摘要翻译： 压控振荡器（4）的振荡频率通过设置设置在锁相环的反馈路径中的可变比分频器（2）的分频比来控制。 当通过改变分频来切换频率时，转向电压（Vda）被施加到压控振荡器。 该转向电压可以补偿非线性，以便在切换之后减少频率误差和相位误差，从而实现高速频率切换。
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公开(公告)号：EP0272938A3
公开(公告)日：1990-03-07
申请号：EP87311404.5
申请日：1987-12-23
IPC分类号： H03L7/18
CPC分类号： H03L7/14 , H03L3/00 , H03L7/0802 , H03L7/10 , H03L7/1972 , H03L7/199
摘要： This invention aims to offsetting the phase difference caused by a delay in a frequency synthesizer which is intermittently actuated for power reduction by setting the division ratio at two levels at the time of releasing reset signals at the variable frequency divider so that the delay time is adjusted by the frequency division in the first cycle. The proposed synthesizer sets the ordinary division ratio in the second cycle and thereafter, and if there is still a phase difference, it sends reset signals again to the variable frequency divider repeating the aforementioned operations. This frequency synthesizer can realise an ideal intermittent operation without significant frequency fluctuation by repeating the above operations to reduce the phase difference at the variable frequency divider to one cycle of the input signals of the counter or less (e.g. ca. 1.3 nsec in 800 MHz).
摘要翻译： 本发明的目的在于通过在释放可变分频器处的复位信号时将分频比设置在两个电平以便延迟时间被调节来抵消由频率合成器中的延迟引起的相位差，所述频率合成器被间歇地启动以用于功率降低 通过第一周期的分频。 所提出的合成器在第二周期和之后设置普通分频比，并且如果仍然存在相位差，它将重置信号再次发送到可变分频器，重复上述操作。 通过重复上述操作，该频率合成器可以实现理想的间歇操作而没有显着的频率波动，以将可变分频器处的相位差减小到计数器的输入信号的一个周期或更少（例如，在800MHz中约1.3nsec） 。
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公开(公告)号：EP0272938A2
公开(公告)日：1988-06-29
申请号：EP87311404.5
申请日：1987-12-23
IPC分类号： H03L7/18
CPC分类号： H03L7/14 , H03L3/00 , H03L7/0802 , H03L7/10 , H03L7/1972 , H03L7/199
摘要： This invention aims to offsetting the phase difference caused by a delay in a frequency synthesizer which is intermittently actuated for power reduction by setting the division ratio at two levels at the time of releasing reset signals at the variable frequency divider so that the delay time is adjusted by the frequency division in the first cycle. The proposed synthesizer sets the ordinary division ratio in the second cycle and thereafter, and if there is still a phase difference, it sends reset signals again to the variable frequency divider repeating the aforementioned operations. This frequency synthesizer can realise an ideal intermittent operation without significant frequency fluctuation by repeating the above operations to reduce the phase difference at the variable frequency divider to one cycle of the input signals of the counter or less (e.g. ca. 1.3 nsec in 800 MHz).
摘要翻译： 本发明旨在通过在释放可变分频器上的复位信号时将分频比设定为两个电平来抵消由频率合成器中的延迟引起的相位差，该频率合成器通过在可变分频器上释放复位信号时将分频比设置为两个电平，从而调整延迟时间 通过第一周期的分频。 所提出的合成器在第二周期中设定普通分频比，之后，如果还存在相位差，则再次将复位信号发送到可重复上述操作的可变分频器。 该频率合成器可以通过重复上述操作来实现无明显频率波动的理想的间歇操作，以将可变分频器的相位差减小到计数器的输入信号的一个周期（例如，800MHz的约1.3nsec） 。
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公开(公告)号：EP0552601B1
公开(公告)日：1996-11-13
申请号：EP93100085.5
申请日：1993-01-05
CPC分类号： G01R25/08 , H03D13/001 , H03L7/091 , H03L7/183
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公开(公告)号：EP0272938B1
公开(公告)日：1994-11-30
申请号：EP87311404.5
申请日：1987-12-23
IPC分类号： H03L7/18
CPC分类号： H03L7/14 , H03L3/00 , H03L7/0802 , H03L7/10 , H03L7/1972 , H03L7/199
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公开(公告)号：EP0552601A2
公开(公告)日：1993-07-28
申请号：EP93100085.5
申请日：1993-01-05
CPC分类号： G01R25/08 , H03D13/001 , H03L7/091 , H03L7/183
摘要： A modulus counter (13B) counts first clock pulses (PCK1) to modulus M and ouputs the count value (Cm) as an m-bit reference signal (S R ), M being an integer. A latch circuit (14) samples and holds the reference signal in response to a trigger signal (Tr) generated by a trigger signal generator (17) in synchronism with an input signal (Sx). A high-speed counter (16) is supplied with second clock pulses (PCK2) of a frequency higher than that of the first clock pulses and starts counting the second clock pulses in response to the trigger signal and stops the counting in response to a first one of the first clock pulses immediately thereafter. A data processor (18) converts the n-bit count value (Cn) of the high-speed counter to n-bit data corresponding to a phase fraction of a phase quantization step in the latch, combines the n-bit data as low-order bits with m-bit data from the latch and outputs the combined data as phase difference data.
摘要翻译： 模数计数器（13B）将第一时钟脉冲（PCK1）计数为模数M，并将计数值（Cm）输出为m位参考信号（SR），M为整数。 锁存电路（14）响应于与输入信号（Sx）同步的由触发信号发生器（17）产生的触发信号（Tr），对参考信号进行采样和保持。 高速计数器（16）被提供有比第一时钟脉冲高的频率的第二时钟脉冲（PCK2），并且响应于触发信号开始对第二时钟脉冲进行计数，并响应于第一时钟脉冲 其后的第一个时钟脉冲之一。 数据处理器（18）将高速计数器的n比特计数值（Cn）转换成与锁存器中的相位量化步长的相位分数对应的n比特数据，将n比特数据组合成低 来自锁存器的m位数据的顺序位，并输出组合数据作为相位差数据。
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