摘要:
A phase locked loop (10) comprising: a tuneable oscillator (12); a mixer-based phase sensitive detector (18) to receive input signals from the tuneable oscillator (12) and a reference signal (20); a cycle slip detector (26) to receive input signals from the tuneable oscillator (12) and the reference signal (20), the cycle slip detector (26) being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals; coarse tune signal means (32, 34) to receive the output signal generated by the cycle slip detector; and adding means (24) for adding a signal output by the coarse signal means (32, 34) to a signal output by the phase sensitive detector (18) to control the frequency of the tuneable oscillator (12).
摘要:
A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.
摘要:
The invention relates to a phase located loop (PLL) synthesiser (1) comprising a phase detector (2), at least one a switchable filter (3), a control voltage (uPLL) controllable oscillator (4) and a programmable divisor (5). The VCO (4) comprises two inputs, wherein the control voltage (uPLL) and a selection voltage (uSET) are applied to the first and second input, respectively, for frequency rough adjustment and determine the VCO (4) frequency.
摘要:
A reduced lock time phase locked loop has a speed up circuit with an operational amplifier (24) to amplify a differential voltage across a filter resistor (R1) of an RC noise filter, the RC noise filter (R1,C) coupling a coarse tune voltage to a VCO (12). The amplified differential voltage is applied to the bases of a pair of opposite polarity transistors (Q1,Q2), the emitters of the transistors being coupled to a filter capacitor (C) in the RC noise filter for rapid charging/discharging. Alternatively the amplified differential voltage is applied to a pair of parallel, opposite polarity diodes (D1,D2) coupled to the filter capacitor for rapid charging/discharging.
摘要:
Gegenstand der Erfindung ist ein Verfahren zum Regeln der von einem frequenzsteuerbaren Oszillator 1 abgegebenen Ausgangsfrequenz, deren Abweichung von einer Soll- oder Referenzfrequenz als Abstimmung an den Oszillator 1 abgegeben wird. Beim Abweichen der Abstimmung von einem vorgegebenen Wert wird ein den Frequenzbereich der Ausgangsfrequenz bestimmendes Abgleichsignal an den Oszillator 1 abgegeben, das den Frequenzbereich in vorgebbaren Zeitabständen, fortlaufend und/oder ereignisgesteuert korrigiert. Ein frequenzsteuerbarer Oszillator 1 zur Durchführung dieses Verfahrens weist mindestens ein mechanisch oder elektrisch beeinflußbares Frequenzstellglied zum Einstellen der vom Oszillator 1 abgegebenen Ausgangsfrequenz und eine Phasenregelschleife 2 auf, die ein die Abweichung der Ausgangsfrequenz von einer Soll- oder Referenzfrequenz entsprechendes Abstimmsignal an einen Abstimmeingang 10 des Oszillators 1 abgibt. Ein mit dem Frequenzstellglied verbundener Abgleicheingang 11 des Oszillators 1 ist an ein integrierendes Stellglied 6 angeschlossen ist, das über einen Schwellwert-Vergleicher 4 mit dem von der Phasenregelschleife 2 abgegebenen Abstimmwert beaufschlagt ist.
摘要:
The invention relates to a method for starting a radio transmitter. In the method a transmission frequency is generated by a phase/frequency-locked loop which comprises a phase/frequency comparator (101), a loop filter (102) and a voltage-controlled oscillator (105), and the start-up is performed by switching on an operating voltage (Ucc) to the voltage-controlled oscillator (105). To minimize the frequency error of the transmitter at the start-up, measuring data about relationship between the control voltage (Vc) of the oscillator and the output frequency (VCOFreq) of the oscillator at a specified calibration temperature are pre-stored in connection with the oscillator, and immediately before switching on the operating voltage (Ucc), control voltage (Vc) needed for locking onto the selected output frequency at the prevailing temperature is estimated and the estimated control voltage is set as the control voltage of the oscillator.