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    Schaltungsanordnung zur Erzeugung komplementärer Signale
    32.
    发明公开
    Schaltungsanordnung zur Erzeugung komplementärer Signale 有权
    沙尔松山（Zur Erzeugungkomplementärer）信号

    公开(公告)号：EP0957582A1

    公开(公告)日：1999-11-17

    申请号：EP99109452.5

    申请日：1999-05-11

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Heyne, Patrick ,  Graetz, Thoralf ,  Haerle, Dieter ,  Johnson, Bret

    IPC分类号： H03K5/151

    CPC分类号： H03K5/151

    摘要： Die vorliegende Erfindung betrifft eine Schaltungsanordnung zur Erzeugung komplementärer Signale, bei der ein Eingangssignal (IN) von einem Eingangsanschluß (5) in einem ersten Zweig über ein Paßglied (2) zu einem ersten Ausgangsanschluß (7) und in einem zum ersten Zweig parallel liegenden zweiten Zweig über einen Inverter (1) zu einem zweiten Ausgangsanschluß (6) geführt ist. Der erste und der zweite Ausgangsanschluß (7, 6) sind über eine Ausgleicheinrichtung (8) mit einem ersten bzw. zweiten Ausgangsknoten (CLKN, CLKP) verbunden, wobei diese Ausgleicheinrichtung (8) die unterschiedlichen Zeitverzögerungen der Signale (C2, C1) im ersten und im zweiten Zweig ausgleicht.

    摘要翻译： 信号发生器包括第一分支，其中输入信号（IN）从输入连接（5）通过通过元件（2）馈送到第一输出连接（7）。 存在与第一分支并联的第二分支，其中输入信号经由逆变器（1）馈送到第二输出连接（6）。 第一和第二输出连接通过均衡装置（8）与第一和第二输出节点（CLKN，CLKP）馈送，其中均衡装置使第一和第二分支中的信号的不同时间延迟相等。

    A circuit and method for generating clock signals
    33.
    发明公开
    A circuit and method for generating clock signals 失效
    电路和方法，用于产生时钟信号

    公开(公告)号：EP0847140A2

    公开(公告)日：1998-06-10

    申请号：EP97121764.1

    申请日：1997-12-05

    申请人： Texas Instruments Incorporated

    发明人： Jones, Jason A. T. ,  Swoboda, Gary L.

    IPC分类号： H03K5/151

    CPC分类号： H03K5/1515

    摘要： A method is provided for forming non-overlapping clock signals 402 and 404 for an integrated circuit. A reference clock 300 whose frequency is twice that of a desired operating frequency for the integrated circuit is used. A master clock signal is formed which has a high pulse width T9a which is approximately the same as the high pulse width of the reference clock, but the frequency of the master clock is one half the frequency of the reference clock. Likewise, a slave clock signal is formed which has a high pulse width T10a which is approximately the same as the high pulse width of the reference clock, but the frequency of the slave clock is also one half the frequency of the reference clock. The high pulse width of either or both the master clock signal and slave clock signal is then widened by an analog delay means, but by an amount T13 and T14 which is less than the low pulse width of the reference clock, so that the master clock signal and the slave clock signal do not overlap each other. As the propagation time of circuit elements within the integrated circuit varies due to changes in operating temperature or voltage, the analog delay T13 and T14 is changed proportionally to compensate for the changes in propagation time of the circuit elements.

    Variable delay circuit
    34.
    发明公开
    Variable delay circuit 失效
    可变延迟电路

    公开(公告)号：EP0709960A3

    公开(公告)日：1997-03-19

    申请号：EP95307414.3

    申请日：1995-10-18

    申请人： Oki Electric Industry Co., Ltd.

    发明人： Yamada, Hiroyuki, c/o Oki Electric Ind Co, Ltd ,  Seki, Shouhei, c/o Oki Electric Ind Co, Ltd

    IPC分类号： H03K5/13 ,  H03K5/151

    CPC分类号： H03K5/151 ,  H03K5/133

    摘要： A variable delay circuit (10) capable of changing delay time includes a latch circuit (13) constituted of a pair of inverters (17,18) cross-coupled to each other and a transistor (16) serving for reducing the voltage difference between the two inputs of the latch circuit (13) based on a control signal (CT) applied thereto. The control signal is also supplied to a pair of transfer gates (14,15) to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor (16) is coupled, and each of which are coupled to further respective transfer gates' output, at which point a respective buffer (11,12) is coupled to feed the output signals. When the control signal (CT) becomes a high level, the state of the transistor (16) becomes low impedance, so that the voltage difference between the two inputs of the latch circuit (13) is reduced, and so that the state of the latch circuit can be quickly and easily changed with small energy. The variable delay circuit can set a minimum delay time smaller than that of the conventional delay circuit, allowing the variable range of delay time to be greater.

    摘要翻译： 一种能够改变延迟时间的可变延迟电路（10）包括：由彼此交叉耦合的一对反相器（17,18）和用于减小在两个晶体管之间的电压差的晶体管（16）组成的锁存电路 基于对其施加的控制信号（CT）的锁存电路（13）的两个输入。 控制信号还被提供给一对传输门（14,15）以控制可变延迟电路的延迟时间。 锁存器电路具有两个输入端，晶体管（16）耦合在这两个输入端之间，并且每个输入端耦合到另外的各个传输门的输出端，此时相应的缓冲器（11,12）被耦合以馈送输出信号。 当控制信号（CT）变为高电平时，晶体管（16）的状态变为低阻抗，使得锁存电路（13）的两个输入之间的电压差减小，并且使得 锁存电路可以快速轻松地以小能量改变。 可变延迟电路可以设置比常规延迟电路小的最小延迟时间，从而允许延迟时间的可变范围更大。

    DRIVER CIRCUIT FOR LOW VOLTAGE DIFFERENTIAL SIGNALING, LVDS, LINE DRIVER ARRANGEMENT FOR LVDS AND METHOD FOR OPERATING AN LVDS DRIVER CIRCUIT
    35.
    发明公开
    DRIVER CIRCUIT FOR LOW VOLTAGE DIFFERENTIAL SIGNALING, LVDS, LINE DRIVER ARRANGEMENT FOR LVDS AND METHOD FOR OPERATING AN LVDS DRIVER CIRCUIT 审中-公开

    公开(公告)号：EP3934096A1

    公开(公告)日：2022-01-05

    申请号：EP20182953.8

    申请日：2020-06-29

    申请人： AMS AG

    发明人： Girani, Elisa ,  Ruck, Dominik

    IPC分类号： H03K5/151 ,  H03K19/094

    摘要： In one embodiment a driver circuit for low voltage differential signaling, LVDS, comprises a phase alignment circuit (20) comprising an input (21) configured to receive an input signal (Vin), a first output (22) configured to provide an internal signal (Vint) as a function of the input signal (Vin), and a second output (23) configured to provide an inverted internal signal (VintN), which is the inverted signal of the internal signal (Vint), and an output driver circuit (30) coupled to the phase alignment circuit (20), the output driver circuit (30) comprising a first input (31) configured to receive the internal signal (Vint), a second input (32) configured to receive the inverted internal signal (VintN), a first output (33) configured to provide an output signal (Vout) as a function of the internal signal (Vint) and a second output (34) configured to provide an inverted output signal (VoutN) which is the inverted signal of the output signal (Vout). Therein the phase alignment circuit (20) is configured to provide the inverted internal signal (VintN) with its phase being aligned to a phase of the internal signal (Vint).

    DEAD-TIME GENERATING CIRCUIT AND MOTOR CONTROL APPARATUS
    39.
    发明授权
    DEAD-TIME GENERATING CIRCUIT AND MOTOR CONTROL APPARATUS 有权
    死时间发生电路和电机控制装置

    公开(公告)号：EP2476195B8

    公开(公告)日：2018-03-28

    申请号：EP10815437.8

    申请日：2010-09-03

    申请人： Ricoh Company, Ltd.

    发明人： UEDA, Yasuo ,  TOKUDA, Masashi ,  TSUKAGOSHI, Toshihiro

    IPC分类号： H02M1/38 ,  H03K5/151 ,  H03K17/16 ,  H02M7/537

    CPC分类号： H02M1/38 ,  H03K5/1515 ,  H03K17/16

    摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

    SINGLE-ENDED-TO-DIFFERENTIAL CONVERTER
    40.
    发明公开
    SINGLE-ENDED-TO-DIFFERENTIAL CONVERTER 审中-公开
    单端至差分转换器

    公开(公告)号：EP3267582A1

    公开(公告)日：2018-01-10

    申请号：EP16199007.2

    申请日：2016-11-16

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： Lee, Yeong-Sheng

    IPC分类号： H03K5/151 ,  H03K5/135 ,  H03K5/156

    CPC分类号： H03K17/6872 ,  H03K5/135 ,  H03K5/151 ,  H03K5/1565

    摘要： A single-ended-to-differential converter (200) for driving an LVDS (Low Voltage Differential Signaling) driving circuit (fig. 1: 140) includes a first converting circuit (210), a second converting circuit (220), and a controller (230). The first converting circuit converts an input signal (SIN) into a first output signal (SOUT1). The first converting circuit (210) has a tunable delay time. The second converting circuit (220) converts the input signal into a second output signal. The second converting circuit (220) has a fixed delay time. The controller (230) generates a first control signal (SC1) and a second control signal (SC2) according to the first output signal (SOUT1) and the second output signal (SOUT2), so as to adjust the tunable delay time of the first converting circuit (210).

    摘要翻译： 用于驱动LVDS（低压差分信号）驱动电路（图1：140）的单端至差分转换器（200）包括第一转换电路（210），第二转换电路（220）和 控制器（230）。 第一转换电路将输入信号（SIN）转换为第一输出信号（SOUT1）。 第一转换电路（210）具有可调延迟时间。 第二转换电路（220）将输入信号转换为第二输出信号。 第二转换电路（220）具有固定的延迟时间。 控制器230根据第一输出信号SOUT1与第二输出信号SOUT2产生第一控制信号SC1与第二控制信号SC2，以调整第一输出信号SOUT1与第二输出信号SOUT2的可调延迟时间， 转换电路（210）。