公开(公告)号：EP0254602B1

公开(公告)日：1992-10-07

申请号：EP87401164.6

申请日：1987-05-22

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： G06F12/06 ,  G11C17/08

CPC分类号： G11C17/08 ,  G06F12/0638 ,  Y02D10/13

摘要： A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.

公开(公告)号：EP0254602A3

公开(公告)日：1990-05-02

申请号：EP87401164.6

申请日：1987-05-22

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： G06F12/06 ,  G11C17/08

CPC分类号： G11C17/08 ,  G06F12/0638 ,  Y02D10/13

摘要： A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.

公开(公告)号：EP0262995A2

公开(公告)日：1988-04-06

申请号：EP87401833.6

申请日：1987-08-06

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： H03K5/153 ,  G11C8/00

CPC分类号： G11C8/18 ,  H03K5/1534

摘要： A signal transition detection circuit comprises a decoder circuit (I) for decoding a plurality of signals, delay circuits (2) having a rise delay time period and a fall time period which are different from each other, and a logic circuit (3). The logic circuit performs a logic operation upon the outputs of the delay circuit to generate a pulse signal (ATD) for indicating at least one transition of the signals.

摘要翻译： 一种信号转换检测电路包括用于信号的多个解码的解码器电路（1），（2），其具有的上升时间段和下降时间段其由海誓山盟不同，和逻辑电路的延迟电路装置（3）。 逻辑电路（3）执行在所述延迟电路装置（2），以产生用于指示所述信号的至少一个转变的脉冲信号（ATD）的输出中操作的逻辑。

公开(公告)号：EP1168365A3

公开(公告)日：2004-09-29

申请号：EP01117838.1

申请日：1992-12-09

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Kawashima, Hiromi ,  Takeguchi, Tetsuji ,  Hagiwara, Ryoji ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawamura, Shouichi ,  Ogawa, Yasushige c/o Fujitsu VLSI Ltd.,

IPC分类号： G11C16/06 ,  H03K19/21 ,  G11C5/14 ,  G11C16/30

CPC分类号： G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

摘要： A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (V BB ). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (V BB ).

公开(公告)号：EP1158534B1

公开(公告)日：2004-06-16

申请号：EP01109454.7

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/30 ,  G11C16/12

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1118937A3

公开(公告)日：2002-08-14

申请号：EP01109451.3

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C29/00

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1158536A2

公开(公告)日：2001-11-28

申请号：EP01109449.7

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/26 ,  G11C16/34

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of nonvolatile memory cells (MCs) each formed of a MIS transistor disposed at an intersection of the word lines and bit lines. A threshold voltage of each MIS transistor is externally electrically controllable. A write circuit (106) is provided for writing data to a memory cell located at an intersection of selected ones of the word lines and bit lines, and a sense amplifier (107) is provided for reading data out of the selected memory cells. The sense amplifier is arranged to change its output current according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.

公开(公告)号：EP1158535A2

公开(公告)日：2001-11-28

申请号：EP01109455.4

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/16 ,  G11C16/34

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and a memory cell array including a plurality of memory cells (MCs) each formed of a MIS transistor disposed at an intersection of a word line with a bit line. The threshold voltage of each MIS transistor is externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors are arranged to be simultaneously discharged to collectively erase the memory cells. The invention provides means for saving overerased memory cells of the semiconductor memory device, detecting memory cells that have been overerased by the collective erasing, and writing data to the overerased memory cells, thereby saving them.

公开(公告)号：EP1158534A2

公开(公告)日：2001-11-28

申请号：EP01109454.7

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/12 ,  G11C16/30

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device (801) having a first terminal (805) for receiving a normal voltage (Vcc) from a normal voltage supply means, and a second terminal (806) for receiving a high voltage (Vpp) from a high-voltage supply means (802), the high voltage (Vpp) being required to write or erase data and higher than the normal voltage (Vcc) required to read data. The semiconductor memory device comprises a third terminal (807) for providing the high-voltage supply means (802) with a control signal that controls the supply of said high voltage. In this way, the two voltage supplies become easy to use and operable like a single supply means.

公开(公告)号：EP1158531A2

公开(公告)日：2001-11-28

申请号：EP01109450.5

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/08

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and nonvolatile memory cells (MCs) formed of a MIS transistor disposed at each intersection of the word lines and bit lines. A threshold voltage of each MIS transistor is externally electrically controllable. A write circuit (106) is provided for writing data to a memory cell located at an intersection of selected ones of the word lines and bit lines, and a sense amplifier (107) is provided for reading data out of the memory cells. The invention provides means for controlling each word line such that a drain current of a memory cell transistor connected to a word line is lower than a channel current thereof, when writing data to the cell transistor, to increase the threshold voltage of the memory cell transistor higher than the potential of an unselected word line.

摘要翻译： 一种具有多个字线（WL），多个位线（BL）和非易失性存储单元（MC）的半导体存储装置，该MIS存储单元由设置在字线和位线的每个交叉处的MIS晶体管形成。 每个MIS晶体管的阈值电压可从外部电控制。 提供写电路（106），用于将数据写入位于字线和位线中被选择的字线和交叉点处的存储单元，并且提供读出放大器（107）用于从存储单元中读出数据。 本发明提供了用于控制每个字线的装置，使得当将数据写入单元晶体管时，连接到字线的存储单元晶体管的漏极电流低于其沟道电流，从而增加存储单元晶体管的阈值电压 高于未选字线的电位。