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232 条记录 (耗时 0.019 秒)

    Semiconductor memory device having stacked capacitor-tape memory cells
    41.
    发明公开
    Semiconductor memory device having stacked capacitor-tape memory cells 失效
    堆叠存储器单元电容器类型的半导体存储器件。

    公开(公告)号：EP0112670A1

    公开(公告)日：1984-07-04

    申请号：EP83307448.7

    申请日：1983-12-07

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Sato, Kimiaki

    IPC分类号： H01L27/10

    CPC分类号： H01L27/10808

    摘要： in a semiconductor memory device having stacked- capacitor memory cells, the capacitor of each memory cell comprises an electrode (E o ), an insulating layer (6), and a counter-electrode (E 1 ). The electrode (E o ) is connected electrically to a source or drain region of the transfer transistor of the memory cell. To provide a memory-cell structure suitable for memory devices with folded bit lines, the electrode (E o ), the insulating layer (6) and the counter-electrode (E,) extend over a part of a word line (WL 2 ) which is adjacent to a word line (WL 1 ) serving as gate electrode of the transfer transistor and at which no memory cell is formed.

    Semiconductor integrated-circuit device with test circuit
    42.
    发明公开
    Semiconductor integrated-circuit device with test circuit 失效
    Integerierte半导体电路与测试电路。

    公开(公告)号：EP0084260A1

    公开(公告)日：1983-07-27

    申请号：EP82306939.8

    申请日：1982-12-23

    申请人： FUJITSU LIMITED

    发明人： Kabashima, Katsuhiko ,  Takemae, Yoshihiro ,  Nozaki, Shigeki ,  Ohira, Tsuyoshi ,  Miyahara, Hatsuo ,  Kanai, Masakazu ,  Enomoto, Seiji

    IPC分类号： G01R31/28

    CPC分类号： G01R31/26 ,  G06F11/006

    摘要： A semiconductor integrated circuit (IC) I, II device Including therein a test circuit (20). The test circuit operates to distinguish the power source level or ground level occurring at an internal node (N), under testing located inside the semiconductor chip. The test circuit is comprised of a series-connected MIS transistor (24), and MIS diode (25). The gate (22), of the MIS transistor is connected to the internal node (N). The MIS diode is connected to an external input/output (I/O pin (21). The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external 1/0 pin, whichever enables a current to be drawn from the external I/O pin.

    Bit-line pre-charge circuit for a dynamic semiconductor memory device
    43.
    发明公开
    Bit-line pre-charge circuit for a dynamic semiconductor memory device 失效
    位线预充电电路，用于动态半导体存储器。

    公开(公告)号：EP0053877A2

    公开(公告)日：1982-06-16

    申请号：EP81305237.0

    申请日：1981-11-04

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4094

    摘要： Disclosed is a dynamic-type semiconductor memory device comprising a group of sense amplifiers (SA), a plurality of pairs of bit lines (BL, BL ) extending from the sense amplifiers, and a plurality of dynamic-type memory cells (MC) connected to each bit line. Each pair of bit lines is short circuited and then precharged to a high potential level before a reading operation. A control line ( ) activating the sense amplifiers is commonly used as a control line for bringing about the precharging of each pair of bit lines, thereby assisting in attainment of high degree of integration and a high short-circuiting speed.

    Semiconductor buffer circuit
    44.
    发明公开
    Semiconductor buffer circuit 失效
    半导体缓冲放大器电路。

    公开(公告)号：EP0052504A1

    公开(公告)日：1982-05-26

    申请号：EP81305415.2

    申请日：1981-11-16

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Mezawa, Tsutomu ,  Enomoto, Seiji ,  Kabashima, Katsuhiko ,  Nozaki, Shigeki

    IPC分类号： G11C8/00 ,  H03F1/30 ,  H03K19/096

    CPC分类号： G11C11/4076 ,  G11C11/418 ,  H03K19/01735 ,  H03K19/01855

    摘要： A semiconductor buffer circuit which is energisable by a power supply (Vcc,Vss) comprises an input stage (Q1-Q4) for receiving an input clock signal (φ 0 ) and an inverted input clock signal ( φ 0 ). A bootstrap circuit (Q5-Q7), which includes a transistor (Q6) for receiving the output of the input stage circuit, maintains the gate voltage of that transistor at a high level during a standby period. An output circuit (Q8-Q12), including a transistor (Q11) which is switched on and off by the output of the bootstrap circuit, generates an output clock signal (φ 1 ). The circuit is characterised by a current leak circuit (X) which maintains, during the standby period, the voltage of a point (N2) in the semiconductor circuit which is charged during the standby period to a level corresponding to the voltage (Vcc) of the power source. A delay in the output clock signal, which is caused by a fluctuation in the voltage of the power supply during the standby period, is thereby reduced, so that the circuit can be used for fast accessing of a dynamic memory. The current leak circuit (X) may comprise two field-effect transistors (Q13,Q14) connected in series, or various arrangements of field-effect transistors and/or resistors.

    A semiconductor memory device of a dynamic type having a data read/write circuit
    45.
    发明公开
    A semiconductor memory device of a dynamic type having a data read/write circuit 失效
    Dynamische Halbleiterspeicheranordnung mit Data-Lese-Schreib-Schaltung。

    公开(公告)号：EP0037239A2

    公开(公告)日：1981-10-07

    申请号：EP81301269.7

    申请日：1981-03-25

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C7/00 ,  G11C11/24

    CPC分类号： G11C5/066 ,  G11C11/4093

    摘要： The read/write circuit comprises a data output buffer (DOB) connected through a three-state circuit (Qa, Q b ) to a common data input/output terminal (I/O), and a data write-in buffer (DWB) of a dynamic type having a latching function connected between the common data input/output terminal (I/O) and data buses (DB, DB) for providng latched data to the data buses. By utilizing a rise or a fall of a write enable signal (WE) or a column address strobe signal (CAS) applied to the memory device, the three-state circuit (Qa, Q b ) is set to a high impedance state, and then write data is latched into the data write-in buffer (DWB).

    摘要翻译： 读/写电路包括通过三状态电路（Qa，Qb）连接到公共数据输入/输出端（I / O）的数据输出缓冲器（DOB）和数据写入缓冲器（DWB） 具有连接在公共数据输入/输出端子（I / O）和数据总线（DB，DB）之间的锁存功能的动态类型，用于向数据总线提供锁存数据。 通过利用施加到存储器件的写使能信号（WE）或列地址选通信号（CAS）的上升或下降，三态电路（Qa，Qb）被设置为高阻抗状态，然后 写数据被锁存到数据写入缓冲器（DWB）中。

    Semiconductor integrated circuit device including a reference voltage generator feeding a plurality of loads
    46.
    发明公开
    Semiconductor integrated circuit device including a reference voltage generator feeding a plurality of loads 失效
    装置与具有一个集成半导体电路，多个负载供给，参考电压发生器的。

    公开(公告)号：EP0013099A1

    公开(公告)日：1980-07-09

    申请号：EP79302874.7

    申请日：1979-12-12

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Masao

    IPC分类号： H01L27/02 ,  G05F1/46 ,  G05F3/08 ,  G11C11/24

    CPC分类号： H03K19/018507 ,  G05F1/467 ,  G05F3/08 ,  G11C11/4074 ,  G11C11/417

    摘要： A plurality of noise limiters (4X and 4Y) have one end connected to an output of a reference voltage generator (1) and another end of each of which is connected to its corresponding load circuit (2X and 2Y). The value of the impedance of the noise limiters (4X and 4Y) is of the same order or higher than the output impedance of the reference voltage generator circuit (1). Preferably noise cancelling means (7) are also provided coupled between the noise limiters (4X and 4Y) and their load circuits (2X and 2Y). Preferably the noise cancelling means are formed by capacitors (7X and7Y) connected across the loads (2X and 2Y).

    摘要翻译： 噪声限制器（4X和4Y）中的多个具有一端在一参考电压发生器（1），并且每个的所有这一切都连接到其对应的负载电路（2X和2Y）的另一端的输出端连接到。 噪声限制器（4X和4Y）的阻抗的值是相同的顺序的或大于参考电压生成器电路（1）的输出阻抗高。 所以优选地噪声消除装置（7）被提供耦合在所述噪声限制器（4X和4Y）及其负载电路（2X和2Y）之间。 优选地消除装置中的噪声是由跨负载（2X和2Y）连接的电容器（7X和7Y）形成。

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    47.
    发明公开
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    带有输入/输出接口的半导体集成电路，适用于小幅度工作

    公开(公告)号：EP0883248A2

    公开(公告)日：1998-12-09

    申请号：EP98114376.1

    申请日：1993-06-14

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao ,  Eto, Satoshi ,  Takemae, Yoshihiro ,  Koga, Makoto ,  Yoshioka, Hiroshi

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018585

    摘要： An input circuit is described for accepting different types of input signals.
    An instruction means (14,86) selects a first mode when an input reference signal is given, and a second mode when it is not. In the first mode, the input voltage is compared with the input reference signal, whereas in the second mode the threshold is a predetermined threshold.

    摘要翻译： 描述了用于接受不同类型的输入信号的输入电路。 指令装置（14,86）在给出输入参考信号时选择第一模式，当给出输入参考信号时选择第二模式。 在第一模式中，将输入电压与输入参考信号进行比较，而在第二模式中，阈值是预定阈值。