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    Enhanced look-up table signal processing
    43.
    发明公开
    Enhanced look-up table signal processing 有权
    Signalverarbeitung mit verb desserten Verweistabellen

    公开(公告)号：EP2101258A1

    公开(公告)日：2009-09-16

    申请号：EP08152533.9

    申请日：2008-03-10

    Applicant: Mobileye Technologies Limited

    Inventor： Navon, Mois ,  Kreinin, Yossi ,  Sixou, Emmanuel ,  Sajman, Roman

    IPC: G06F9/345 ,  G06F9/38

    CPC classification number: G06F9/345 ,  G06F9/3004 ,  G06F9/3824

    Abstract: An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter ( e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.

    Abstract translation: 一种包括存储数据的可寻址寄存器阵列的电子设备。 连接到阵列的输入寄存器在连接到可寻址寄存器阵列的一个或多个输入寄存器中存储输入命令参数（例如命令的操作码）及其相关联的操作数。 命令的单个实例访问阵列的至少一个寄存器。 基于输入命令参数，所有地址操作数的命令：读取先前存储在至少一个寄存器中的数据的数据，更新数据，从而产生更新的数据，并将更新的数据写入至少一个寄存器。 该命令具有引用一个或多个寄存器的多个地址操作数，并支持两个或多个地址操作数相同。 该装置包括向处理电路提供逻辑输出信号的逻辑电路，指示地址操作数中的哪一个（如果有的话）是相同的。 基于逻辑输出的处理电路在将更新的数据写入至少一个寄存器之前首先处理任何相同的地址操作数，使得命令的新实例在处理电路上以连续的时钟脉冲和指令吞吐量开始处理 每个时钟脉冲是一个命令。

    Processor supporting vector mode execution
    47.
    发明公开
    Processor supporting vector mode execution 有权
    DieVektormodusausführungunterstützenderProzessor

    公开(公告)号：EP1942410A2

    公开(公告)日：2008-07-09

    申请号：EP07254379.6

    申请日：2007-11-06

    Applicant: STMicroelectronics, Inc

    Inventor： Colavin, Osvaldo M.

    IPC: G06F9/30

    CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

    Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

    Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，则耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重新命名寄存器地址，以确保在向量运行中正确执行捆绑。 另外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

    SCALABLE MULTI-THREADED MEDIA PROCESSING ARCHITECTURE
    48.
    发明公开
    SCALABLE MULTI-THREADED MEDIA PROCESSING ARCHITECTURE 有权
    SKALIERBARE MEHRFACH-THREAD-MEDIENVERARBEITUNGSARCHITEKTUR

    公开(公告)号：EP1932077A2

    公开(公告)日：2008-06-18

    申请号：EP06779565.8

    申请日：2006-09-26

    Applicant: Imagination Technologies Limited

    Inventor： HOWSON, John

    IPC: G06F9/38 ,  G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/3851 ,  G06F9/3824 ,  G06F9/5011 ,  G06F2209/507

    Abstract: A method and apparatus are provided for processing multiple streams of data on a plurality of execution threads. Data is selected from a plurality of data sources. An address in the data storage device is allocated for the selected data which is loaded into the allocated address. An execution task including the selected data source, the data address and an execution address is constructed and the data task is queued with previously constructed tasks. A determination is made as to which processing resources are required for each task and tasks are selected for execution in dependence on the determination. Tasks selected for execution are distributed across a plurality of processing threads.

    Abstract translation: 提供一种用于在多个执行线程上处理多个数据流的方法和装置。 从多个数据源中选择数据。 数据存储装置中的地址被分配给被加载到分配的地址中的所选择的数据。 构建包括所选数据源，数据地址和执行地址的执行任务，并且数据任务与先前构造的任务排队。 确定每个任务需要哪些处理资源，并且根据确定选择任务执行。 选择执行的任务分布在多个处理线程中。

    Access method and access circuit for flash memory in embedded system
    49.
    发明公开
    Access method and access circuit for flash memory in embedded system 审中-公开
    方法和电路，用于在嵌入式系统中访问闪速存储器

    公开(公告)号：EP1785843A3

    公开(公告)日：2008-05-14

    申请号：EP06000355.5

    申请日：2006-01-10

    Applicant: Cheertek Inc.

    Inventor： Hsu, Chin-Fu

    IPC: G06F9/38 ,  G11C7/10

    CPC classification number: G11C7/1015 ,  G06F9/3824 ,  G06F9/3879 ,  G11C16/102 ,  G11C2207/104

    Abstract: The present invention relates an access method for flash memory in an embedded system, including the following steps: divide the flash memory into a main program zone and a storage zone; provide an access circuit having a command register for receiving commands and a microcontroller status buffer; the access circuit detects if the microcontroller executes the command to access the storage zone and, if not, continues to detect; when the microcontroller executes the command to access the storage zone, the access circuit stores the command in the command register for receiving commands, stores the status of the microcontroller in the microcontroller status buffer, and executes the read/write command for the storage zone; the access circuit stores the results of the read/write commands in the command register for receiving commands; and the access circuit retrieves the status of the microcontroller from the microcontroller status buffer to return the microcontroller to its original status to continuously execute access commands. In addition, the present discloses an access circuit which can be used by a microcontroller of an embedded system to read/write external flash memory.

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