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147 条记录 (耗时 0.013 秒)

    High speed logic circuit
    41.
    发明公开
    High speed logic circuit 失效
    高速逻辑电路

    公开(公告)号：EP0337078A3

    公开(公告)日：1990-05-09

    申请号：EP89102647.8

    申请日：1989-02-16

    申请人： HONEYWELL INC.

    发明人： Fulkerson, David E.

    IPC分类号： H03K19/017

    CPC分类号： H03K19/0013 ,  H03K19/01707

    摘要： An improved FET capacitance driver logic circuit has an inverter feedback stage (22) connected from the output to the input of an output FET (23) to allow the output FET to have a large capacitance charging current surge followed by a reduced conduction thereafter.

    Amplifier arrangement, in particular for amplifying a digital signal
    42.
    发明公开
    Amplifier arrangement, in particular for amplifying a digital signal 失效
    Verstärkerschaltung，insbesondere zumVerstärkeneines digitalen信号。

    公开(公告)号：EP0357131A2

    公开(公告)日：1990-03-07

    申请号：EP89202143.7

    申请日：1989-08-24

    申请人： Philips Electronics N.V.

    发明人： Cornelissen, Bernardus Henricus Jozef

    IPC分类号： H03K19/013 ,  H03K19/017 ,  H03F1/08 ,  H03F3/50

    CPC分类号： H03F1/086 ,  H03F3/505 ,  H03K19/013 ,  H03K19/01707

    摘要： The invention relates to an amplifier arrangement comprising a first (T1) and a second (T2) field-effect transistor of the same conductivity type and a driver circuit (Q1, Q2, Q3, T3, T4, T5, I) which is responsive to drive the respective drain electrodes of the two field-effect transistors (T1, T2) to a signal to be amplified and applied to the input terminals (3, 4) drive the respective drain electrodes of the two field-effect transistors (T1, T2). An element (R) having a resistive action is formed between the drain and the gate electrode of the first field-effect transistor (T1) and an element (C) having a capacitive action is formed between the gate and the source electrode. Together with said elements (R, C) the first field-effect transistor (T1) constitutes a reactance circuit having an inductive character, which is arranged in parallel with the parasitic gate-source capacitance of the second field-effect transistor (T2). This results in the step-function response and edge steepness of step-function signals on the output terminal (5) at the drain electrode of the second field-­effect transistor (T2) being improved in comparison with an amplifier arrangement without said reactance circuit. The circuit is very suitable for integration in BICMOS technology.

    摘要翻译： 本发明涉及一种放大器装置，其包括具有相同导电类型的第一（T1）和第二（T2）场效应晶体管和驱动电路（Q1，Q2，Q3，T3，T4，T5，I） 将两个场效应晶体管（T1，T2）的各个漏电极驱动到要放大的信号，并施加到输入端子（3,4）上驱动两个场效应晶体管（T1，T2）的各个漏电极， T2）。 在第一场效应晶体管（T1）的漏极和栅电极之间形成具有电阻作用的元件（R），并且在栅极和源极之间形成具有电容作用的元件（C）。 与所述元件（R，C）一起，第一场效应晶体管（T1）构成具有感应特性的电抗电路，其与第二场效应晶体管（T2）的寄生栅 - 源电容并联布置。 这导致与没有所述电抗电路的放大器装置相比，第二场效应晶体管（T2）的漏极处的输出端子（5）上的步进功能响应和边缘陡峭度得到改善。 该电路非常适合集成在BICMOS技术中。

    Buffer circuit for logic level conversion
    43.
    发明公开
    Buffer circuit for logic level conversion 失效
    Pufferschaltungfürlogische Pegelumsetzung。

    公开(公告)号：EP0356986A2

    公开(公告)日：1990-03-07

    申请号：EP89115900.6

    申请日：1989-08-29

    申请人： FUJITSU LIMITED

    发明人： Kajii, Kiyoshi

    IPC分类号： H03K19/094

    CPC分类号： H03K19/018535 ,  H03K19/00384 ,  H03K19/01707

    摘要： An input buffer circuit for converting a logic level of an input logic signal comprises an inversion circuit (52, 82) and a level shift circuit (23) in which the inversion circuit comprises an input terminal (61) to which the input signal is applied, a first voltage source for supplying a first predetermined voltage, a second voltage source for supplying a second predetermined voltage having a level lower than that of the first predetermined voltage, a first resistor circuit (71) having a first end connected to the first voltage source, a first enhancement type field effect transistor (59) having a drain connected to a second end of the first resistor circuit, a source connected to the second voltage source and a gate connected to the input terminal, a second resistor circuit having a first end connected to the first voltage source, and a second enhancement type field effect transistor (60) having a drain connected to a second end of the second resistor circuit, a source connected to the drain of the first enhancement type field effect transistor and a gate connected to the the gate of the first enhancement type field effect transistor.

    摘要翻译： 用于转换输入逻辑信号的逻辑电平的输入缓冲电路包括反相电路（52,82）和电平移位电路（23），其中反相电路包括施加输入信号的输入端（61） ，用于提供第一预定电压的第一电压源，用于提供具有低于第一预定电压电平的第二预定电压的第二电压源;第一电阻器电路，其第一端连接到第一电压 源极，具有连接到第一电阻器电路的第二端的漏极的第一增强型场效应晶体管（59），连接到第二电压源的源极和连接到输入端子的栅极;第二电阻器电路，具有第一 端部连接到第一电压源，以及第二增强型场效应晶体管（60），其漏极连接到第二电阻器电路的第二端，源极连接到t 第一增强型场效应晶体管的漏极和连接到第一增强型场效应晶体管的栅极的栅极。

    Gallium arsenide gate array integrated circuit including DCFL NAND gate
    46.
    发明公开
    Gallium arsenide gate array integrated circuit including DCFL NAND gate 失效
    阿拉伯盖栅阵列集成电路，包括DCFL NAND门

    公开(公告)号：EP0196391A3

    公开(公告)日：1987-04-08

    申请号：EP85309059

    申请日：1985-12-12

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Ikawa, Yasuo c/o Patent Division ,  Kawakyu, Katsue c/o Patent Division ,  Kameyama, Atushi c/o Patent Division

    IPC分类号： H03K19/173 ,  H03K19/094

    CPC分类号： H03K19/01707 ,  H03K19/0952

    摘要： A gallium arsenide NAND gate (100) is connected between a power source (V DD ) and a ground potential. The gate (100) is comprised of a load transistor (20) of a normally-on type field effect transistor having an output terminal (C) and a drain connected to the power source (V DD ), a first driver transistor (22) of a normally-off type field effect transistor having a gate electrode as a first input terminal (IN,) and a source-to-drain current path series-connected to that of the load transistor (20), and a second driver transistor (24) of two normally-off type field effect transistors (24A, 248) having a common gate electrode for a second input terminal (IN 2 ) and source-to-drain current paths series-connected between the power source (V po ) and the ground potential through the series-connected first driver transistor (22) and load transitor (20). The normally-off type field effect transistors (24A, 24B) are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor (24).

    Output buffer circuit
    47.
    发明公开
    Output buffer circuit 失效
    输出缓冲电路

    公开(公告)号：EP0121217A3

    公开(公告)日：1987-01-28

    申请号：EP84103372

    申请日：1984-03-27

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Yasuda, Hiroshi ,  Ochii, Kiyofumi

    IPC分类号： H03K05/02 ,  H03K19/094

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  H03K19/01707 ,  H03K19/01721

    摘要： An output buffer circuit has a data input terminal (IN) which receives logic data, load and drive transistors (20,22), a driver (24) for selectively turning on the transistors (20, 22) in accordance with the logic value of the logic data, a data output terminal (OUT) which is connected to a power source terminal (VD) of the VDD level through a current path of the load transistor (20) and is grounded through a current path of the drive transistor (22), and a capacitor (26) connected as a load to the data output terminal (OUT). The output buffer circuit further has a transition detector circuit (46) for generating a pulse signal in responseto a change in level of each of address signals (A1 - AN), and a preset circuit (48) for supplying, in response to the pulse signal, a charge or discharge current to the capacitor (26) while a voltage at the data output terminal (OUT) is not at the VDD/2 level.

    Input buffer circuit
    49.
    发明公开
    Input buffer circuit 失效
    输入缓冲电路

    公开(公告)号：EP0110701A3

    公开(公告)日：1985-01-09

    申请号：EP83307239

    申请日：1983-11-28

    申请人： HITACHI, LTD.

    发明人： Masuda, Noboru ,  Asano, Michio ,  Hayashi, Takehisa ,  Tanaka, Hirotoshi ,  Masaki, Akira

    IPC分类号： H03K19/094

    CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

    摘要： An input buffer circuit having a source follower circuit composed of a first FET (Q 1 ) whose gate electrode has an input (V in ) connected thereto, and a second FET (Q 2 ) of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET (Qi) directly or through at least one level-shifting diode (D i ) and whose gate electrode is supplied with a control voltage (V cont ); and a FET inverter circuit (Q 3 , 0 4 ) which is connected to the drain electrode of the second FET directly or through at least one level-shifting diode (D 2 ); an output signal being derived from the FET inverter circuit (Q 3 , Q 4 ).

    Input buffer circuit
    50.
    发明公开
    Input buffer circuit 失效
    输入缓冲电路。

    公开(公告)号：EP0110701A2

    公开(公告)日：1984-06-13

    申请号：EP83307239.0

    申请日：1983-11-28

    申请人： HITACHI, LTD.

    发明人： Masuda, Noboru ,  Asano, Michio ,  Hayashi, Takehisa ,  Tanaka, Hirotoshi ,  Masaki, Akira

    IPC分类号： H03K19/094

    CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/01707 ,  H03K19/018535

    摘要： An input buffer circuit having a source follower circuit composed of a first FET (Q 1 ) whose gate electrode has an input (V in ) connected thereto, and a second FET (Q 2 ) of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET (Qi) directly or through at least one level-shifting diode (D i ) and whose gate electrode is supplied with a control voltage (V cont ); and a FET inverter circuit (Q 3 , 0 4 ) which is connected to the drain electrode of the second FET directly or through at least one level-shifting diode (D 2 ); an output signal being derived from the FET inverter circuit (Q 3 , Q 4 ).