公开(公告)号：EP0669055A1

公开(公告)日：1995-08-30

申请号：EP94901340.0

申请日：1993-11-08

申请人： INFINITE TECHNOLOGY CORPORATION ,  NIPPON PRECISION CIRCUITS INC.

发明人： JENNINGS, Earle, W., III ,  LANDERS, George, Herman

IPC分类号： G06F15 ,  G06F17 ,  H03K19

CPC分类号： H03K19/17704

摘要： A logic system comprising one or more logic networks (LNA0..LNA3) that can perform a variety of logic functions, either by configuration of a multi-function network or by a switched network comprising several sub-networks each of which performs one or more dedicated logic functions. Each logic network is functionally separate from but operatively associated with one or more programmable circuits (PROG) from which that logic network receives logic control signals (LSFA0..LSFA3) to select a particular logic function or functions to be performed by the logic network(s). The programmable circuit also supplies separate logic signals (LSCA0..LSCA3) to control the operation of the logic network(s) in implementing the selected logic function. In this manner the programmable circuit (PROG) can essentially be dedicated to selecting the function and controlling the operation of the selected function of the logic network(s) and is relieved of significant functional overhead associated with data manipulation typically performed by conventional operation of logic network(s). This can permit a smaller size programmable logic, gate or memory array to be used to control a logic operation of a given complexity, or a given size of array to control more complex operations. Both the programmable circuit(s) and the logic network(s) can be integrated in a single semiconductor chip.

公开(公告)号：EP0612154A1

公开(公告)日：1994-08-24

申请号：EP94300948.0

申请日：1994-02-09

申请人： SGS-Thomson Microelectronics Limited ,  CHANCELLOR, MASTERS & SCHOLARS OF THE UNIVERSITY OF OXFORD

发明人： Stansfield, Anthony Ian

IPC分类号： H03K19/177

CPC分类号： H03K19/17796 ,  G11C15/04 ,  H03K19/177 ,  H03K19/17704

摘要： A programmable logic device comprises a plurality of logic circuits interconnected through an interconnection network. Each logic circuit comprises an array (14) of memory cells. The memory cells are in a first mode of operation responsive to an address signal at the location of that cell to output data stored in the cell. In a second mode of operation the memory cells are operable to compare data input to it with data stored in it and to output a match signal when said input data matches said stored data. The programmable logic device comprises circuitry for operating that array of memory cells as a random access memory (RAM) with the cells in the first mode of operation and circuitry for operating that array of memory cells as content addressable memory (CAM) in the second mode of operation.

摘要翻译： 可编程逻辑器件包括通过互连网互连的多个逻辑电路。 每个逻辑电路包括存储器单元的阵列（14）。 存储器单元处于响应于该单元的位置处的地址信号的第一操作模式以输出存储在单元中的数据。 在第二操作模式中，存储器单元可操作以将输入的数据与其中存储的数据进行比较，并且当所述输入数据与所存储的数据匹配时输出匹配信号。 可编程逻辑器件包括用于将存储器单元阵列作为随机存取存储器（RAM）操作的电路，其中处于第一操作模式的单元和用于在第二模式中操作该存储单元阵列作为内容寻址存储器（CAM）的电路 的操作。

公开(公告)号：EP0573152A3

公开(公告)日：1994-04-06

申请号：EP93303647.7

申请日：1993-05-11

申请人： PLESSEY SEMICONDUCTORS LIMITED

发明人： Hastie, Neil Stuart

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors (1,2,3,4), five inverters (12,13,15,16,17) and an OR gate (14) to provide a very fast programmable logic cell.

摘要翻译： 可编程逻辑单元适用于可编程门阵列并能产生两个输入的任何逻辑功能，作为2至1多路复用器或数据锁存器由四个多路复用器（1,2,3,4），五个 反相器（12,13,15,16,17）和一个或门（14），以提供一个非常快速的可编程逻辑单元。

公开(公告)号：EP0585119A1

公开(公告)日：1994-03-02

申请号：EP93306760.5

申请日：1993-08-25

申请人： AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC.

发明人： Crafts, Harold S. ,  McKinley, William W.

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/1778

摘要： A programmable logic device includes a data bus for receiving input data and a serial shift register (30) adapted to receive programming data in the form of a binary serial bit stream (33). Outputs of the shift register (30) control the charges on capacitors (C1,C2) which are connected to inputs of logic gates (1,2) to control the functions implemented by the logic gates. In this manner, selected input variables can be combined in accordance with the charges stored on the capacitors (C1,C2) to enable the logic device to provide a desired Booleon function. The logic device can be readily reprogrammed by changing the programming binary serial bit stream.

摘要翻译： 可编程逻辑器件包括用于接收输入数据的数据总线和适于接收二进制串行比特流（33）形式的编程数据的串行移位寄存器（30）。 移位寄存器（30）的输出控制连接到逻辑门（1,2）的输入的电容器（C1，C2）上的电荷，以控制由逻辑门实现的功能。 以这种方式，可以根据存储在电容器（C1，C2）上的电荷来组合所选择的输入变量，以使得逻辑器件能够提供期望的布尔函数。 逻辑器件可以通过更改编程二进制串行比特流轻松重新编程。

公开(公告)号：EP0584910A1

公开(公告)日：1994-03-02

申请号：EP93305041.1

申请日：1993-06-28

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Agrawal, OM P.

IPC分类号： H03K19/177

CPC分类号： H03K19/17796 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17704

摘要： The programmable logic device (PLD) (100) of this invention includes two or more programmable logic blocks (101) interconnected by a programmable switch matrix that includes a programmable input switch matrix (120) and a programmable centralized switch matrix (130). Each programmable logic block is coupled to a plurality of programmable I/O macrocells (106) by an output switch matrix (140). Each programmable I/O macrocell is connected to one of a plurality of I/O pins for the programmable logic block. In one embodiment, an input macrocell couples an I/O macrocell and the associated I/O pin to the programmable input switch matrix. The programmable input switch matrix provides a uniform treatment of all feedback signals to the programmable centralized switch matrix and thereby simplifies signal routing, provides an improved functionality balance, and improved resource utilization within the PLD. The output switch matrix routes output signals from a programmable logic block to any one of a multiplicity of the I/O macrocells (106A-106H) The output switch matrix and the input switch matrix decouple the programmable logic block and centralized switch matrix from the pin-out and the feedback architecture of the PLD. Thus, the output switch matrix and the input switch matrix may be effectively used with a wide variety of programmable interconnect structures and programmable logic block architectures to achieve enhanced resource utilization, routability and functionality.

摘要翻译： 本发明的可编程逻辑器件（PLD）（100）包括通过包括可编程输入开关矩阵（120）和可编程集中式开关矩阵（130）的可编程开关矩阵互连的两个或多个可编程逻辑块（101）。 每个可编程逻辑块通过输出开关矩阵（140）耦合到多个可编程I / O宏单元（106）。 每个可编程I / O宏单元连接到可编程逻辑块的多个I / O引脚之一。 在一个实施例中，输入宏单元将I / O宏单元和相关联的I / O引脚耦合到可编程输入开关矩阵。 可编程输入开关矩阵提供对可编程集中式开关矩阵的所有反馈信号的均匀处理，从而简化了信号路由，提供了改进的功能平衡，并提高了PLD内的资源利用率。 输出开关矩阵将输出信号从可编程逻辑块路由到多个I / O宏单元（106A-106H）中的任何一个。输出开关矩阵和输入开关矩阵将可编程逻辑块和集中式开关矩阵从引脚 - 和PLD的反馈架构。 因此，输出开关矩阵和输入开关矩阵可以与各种可编程互连结构和可编程逻辑块架构有效地一起使用，以实现增强的资源利用率，可路由性和功能性。

公开(公告)号：EP0555353A4

公开(公告)日：1994-02-16

申请号：EP91920420

申请日：1991-11-01

申请人： CONCURRENT LOGIC, INC.

发明人： CAMAROTA, RAFAEL, C. ,  FURTEK, FREDERICK, C. ,  HO, WALFORD, W. ,  BROWDER, EDWARD, H.

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/17704

公开(公告)号：EP0219221B1

公开(公告)日：1993-12-29

申请号：EP86306966.2

申请日：1986-09-10

申请人： Pilkington Micro-Electronics Limited

发明人： Austin, Kenneth

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  G06F17/5027 ,  H03K5/026 ,  H03K17/687 ,  H03K19/1733 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1778

公开(公告)号：EP0573152A2

公开(公告)日：1993-12-08

申请号：EP93303647.7

申请日：1993-05-11

申请人： PLESSEY SEMICONDUCTORS LIMITED

发明人： Hastie, Neil Stuart

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors (1,2,3,4), five inverters (12,13,15,16,17) and an OR gate (14) to provide a very fast programmable logic cell.

摘要翻译： 可编程逻辑单元适用于可编程门阵列并且能够产生两个输入的任何逻辑功能，作为2至1多路复用器或数据锁存器由四个多路复用器，五个反相器和“或”门形成，以提供非常 快速可编程逻辑单元。

公开(公告)号：EP0287337B1

公开(公告)日：1993-09-15

申请号：EP88303292.2

申请日：1988-04-13

申请人： ROHM CORPORATION

发明人： Goetting, Erich

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K17/22 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/1776

公开(公告)号：EP0486991A3

公开(公告)日：1992-10-28

申请号：EP91119638.4

申请日：1991-11-18

申请人： KAWASAKI STEEL CORPORATION

发明人： Shibata, Keiji

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17704 ,  H03K19/17728

摘要： In a programmable logic device having a memory circuit for storing circuit configuration data and a logic gate block for realizing a logic circuit desired by a user on the basis of the circuit configuration data written into the memory circuit, a switching circuit (20) is provided for controlling at least a part (14) of a circuit (10) for writing the circuit configuration data into the memory circuit so as to be utilized as a part of the logic circuit (12) desired by the user after the circuit configuration.