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    AUTO-SUSPEND AND AUTO-RESUME OPERATIONS FOR A MULTI-DIE NAND MEMORY DEVICE
    43.
    发明公开
    AUTO-SUSPEND AND AUTO-RESUME OPERATIONS FOR A MULTI-DIE NAND MEMORY DEVICE 审中-公开
    多纳米器件的自我暂停和自我接收操作

    公开(公告)号：EP2979270A4

    公开(公告)日：2016-11-09

    申请号：EP14774103

    申请日：2014-02-13

    申请人： INTEL CORP

    发明人： GHALAM ALI ,  NOBUNAGA DEAN ,  GUO JASON

    IPC分类号： G11C16/34 ,  G11C16/30

    CPC分类号： G11C16/30 ,  G06F1/3275 ,  G11C5/148 ,  G11C8/12 ,  G11C16/225 ,  Y02B60/1228 ,  Y02D10/14

    摘要： A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.

    摘要翻译： 一种通过由多芯片存储器的至少一个管芯确定后续存储器操作是否是高电流存储器来控制多管芯存储器（例如固态驱动器）中的峰值电流状态的方法和装置 操作，例如使能芯片的电荷泵的操作，对芯片的位线充电的操作，或编程/擦除循环操作，或其组合。 如果后续存储器操作被确定为高电流存储器操作，则芯片进入暂停操作模式。 响应于恢复操作事件，例如但不限于对芯片的特定地址的命令，来自另一管芯的指示大电流存储器操作完成的操作由管芯复原。 一旦操作恢复，芯片执行高电流存储器操作。

    ACCESSING MEMORY
    46.
    发明公开
    ACCESSING MEMORY 审中-公开
    MEMORY

    公开(公告)号：EP2859457A4

    公开(公告)日：2016-05-11

    申请号：EP12878588

    申请日：2012-06-08

    申请人： HEWLETT PACKARD DEVELOPMENT CO

    发明人： YOON DOE HYUN ,  MURALIMANOHAR NAVEEN ,  CHANG JICHUAN ,  RANGANTHAN PARTHASARATHY

    IPC分类号： G11C5/04 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38 ,  G11C7/10

    CPC分类号： G11C7/1072 ,  G06F13/1663 ,  G11C5/04 ,  G11C2207/108 ,  G11C2207/2209 ,  G11C2207/2281 ,  Y02B60/1228 ,  Y02D10/14

    摘要： A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

    摘要翻译： 所公开的示例性方法包括在至少第一和第二独立可选逻辑子列上执行同时数据访问，以通过存储器设备中的宽内部数据总线访问第一数据。 存储器件包括转换缓冲器芯片，可独立选择的逻辑子级别的存储器芯片，用于将转换缓冲器芯片连接到存储器控制器的窄外部数据总线，以及翻译缓冲器芯片和存储器芯片之间的宽内部数据总线 。 仅通过第一可独立选择的逻辑子级执行数据访问，以经由宽内部数据总线访问第二数据。 示例性方法还包括在单独的数据传输期间将第一数据的第一部分，第一数据的第二部分和窄的外部数据总线上的第二数据定位。

    METHOD AND APPARATUS FOR ALLOCATING INTERRUPTS IN A MULTI-CORE SYSTEM
    48.
    发明公开
    METHOD AND APPARATUS FOR ALLOCATING INTERRUPTS IN A MULTI-CORE SYSTEM 审中-公开
    VERFAHREN UND VORRICHTUNG ZUR ZUWEISUNG VON UNTERBRECHUNGEN IN EINEM MEHRKERNSYSTEM

    公开(公告)号：EP2750045A4

    公开(公告)日：2015-04-08

    申请号：EP12826403

    申请日：2012-08-10

    申请人： SAMSUNG ELECTRONICS CO LTD

    发明人： HAN SANG BOK ,  KIM HONG CHUL ,  YEO IN CHOON ,  PARK JONG-CHUL

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24 ,  Y02B60/1228 ,  Y02D10/14

    摘要： The present invention relates to an apparatus and method for allocating interrupts in a multi-core system. According to one embodiment of the present invention, a method for allocating interrupts of an interrupt allocation apparatus including an interrupt control register unit, which records the interrupt processing capacity of each core of a multi-core system, can comprise: a reception step of receiving an interrupt; a checking step of checking the interrupt control register unit when receiving the interrupt; and an allocation step of allocating the interrupt to a core which has been checked to be in an interrupt processing enabled state in the checking step. When the core is allocated the interrupt, the core transmits, to the interrupt control register unit, a signal representing the interrupt control register corresponding to the core which is changed to an interrupt processing disabled state, and can process the interrupt. According to one embodiment of the present invention, the method for allocating interrupts and apparatus for efficient and rapid interrupt processing in a multi-core system can be provided.

    摘要翻译： 本发明涉及一种用于在多核系统中分配中断的装置和方法。 根据本发明的一个实施例，一种用于分配中断分配装置的中断的方法，包括记录多核系统的每个核的中断处理能力的中断控制寄存器单元，其包括：接收步骤， 中断; 当接收到中断时检查中断控制寄存器单元的检查步骤; 以及分配步骤，用于在检查步骤中将中断分配给已被检查为处于中断处理使能状态的核心。 当核心被分配中断时，核心向中断控制寄存器单元发送一个表示与核心相对应的中断控制寄存器的信号，该中断控制寄存器改变为中断处理禁止状态，并且可以处理中断。 根据本发明的一个实施例，可以提供用于分配中断的方法和用于多核系统中的高效快速中断处理的装置。