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    DEMULTIPLEXING CIRCUIT, MULTIPLEXING CIRCUIT, AND CHANNELIZER RELAY UNIT
    41.
    发明公开
    DEMULTIPLEXING CIRCUIT, MULTIPLEXING CIRCUIT, AND CHANNELIZER RELAY UNIT 审中-公开

    公开(公告)号：EP3595173A1

    公开(公告)日：2020-01-15

    申请号：EP18764164.2

    申请日：2018-03-05

    申请人： Mitsubishi Electric Corporation

    发明人： TAKEMOTO, Yuta ,  FUJIMURA, Akinori ,  YAMAMOTO, Yuichi

    IPC分类号： H03H17/00 ,  H03H17/02 ,  H04J1/05

    摘要： A multi-stage demultiplexing circuit in which a plurality of circuits each combining a selector and a frequency decimation circuit are connected is included. The selector selects one of input signals based on a control signal, and generates a plurality of output signals. The plurality of output signals output from the selector are input to the frequency decimation circuit, and the frequency decimation circuit performs frequency conversion processing, low pass filter processing, and down-sampling processing based on a control signal to generate an output signal. Two or more reception signals are input to the multi-stage demultiplexing circuit, and the multi-stage demultiplexing circuit executes demultiplexing processing based on a control signal so that an output signal that includes an unused band portion is prevented from being output downstream.

    METHOD AND APPARATUS FOR SAMPLING RATE CONVERSION OF A STREAM OF SAMPLES
    42.
    发明公开
    METHOD AND APPARATUS FOR SAMPLING RATE CONVERSION OF A STREAM OF SAMPLES 审中-公开

    公开(公告)号：EP3466004A1

    公开(公告)日：2019-04-10

    申请号：EP17727205.1

    申请日：2017-05-31

    申请人： OCTO Telematics S.p.A.

    发明人： AVANTAGGIATI, Vito ,  AMENDOLAGINE, Marco

    IPC分类号： H04L25/05 ,  H03H17/00 ,  H03H17/06

    摘要： A method of converting a stream of samples at a first sampling rate to a stream of samples at a second sampling rate is disclosed, comprising: measuring the first sampling rate; determining a first upsampling factor from a basis comprising: the measured first sampling rate, the target value of the second sampling rate, and a resynchronisation error factor, the first upsampling factor being constrained to be an integer power of a predetermined integer value; and deriving, from a reference set of filter coefficients and from a ratio of the first upsampling factor to a reference upsampling factor, a first set of filter coefficients for use in a first interpolation filter, the reference set of filter coefficients being for a reference upsampling factor that is an integer power of the predetermined integer value.

    LOW-POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING PRIMARY SIDEBAND FILTERS ALIGNED WITH PHASE OF 180° AND HAVING REDUCED JITTER ACCORDING TO PHASE OF SIDEBAND DIFFERENTIAL OUTPUT COMPARATORS
    45.
    发明公开
    LOW-POWER WIDEBAND ASYNCHRONOUS BINARY PHASE SHIFT KEYING DEMODULATION CIRCUIT USING PRIMARY SIDEBAND FILTERS ALIGNED WITH PHASE OF 180° AND HAVING REDUCED JITTER ACCORDING TO PHASE OF SIDEBAND DIFFERENTIAL OUTPUT COMPARATORS 审中-公开
    低功率宽带异步二值相移键控解调电路使用初级侧带滤波器进行180°相位调整，并根据边带差分输出比较器的相位进行降低抖动

    公开(公告)号：EP3208984A1

    公开(公告)日：2017-08-23

    申请号：EP15850547.9

    申请日：2015-10-15

    申请人： Wilkerson, Benjamin P.

    发明人： Wilkerson, Benjamin P.

    IPC分类号： H04L27/233 ,  H03H17/00

    CPC分类号： H04L27/233 ,  H03K5/2481 ,  H03K19/01728 ,  H03K19/01855 ,  H03K19/0963 ,  H04L7/0278 ,  H04L27/2331 ,  H04L27/2334 ,  H04L27/2335 ,  H04W4/80

    摘要： An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit for separating a modulated signal into an upper sideband and a lower sideband using a primary high pass filter, which has a carrier frequency as the cutoff frequency thereof, and a primary low pass filter and digitalizing the same into a positive phase and a negative phase such that, in connection with a digital output from a lower sideband comparator and a digital output from an upper sideband comparator, signals with opposite phases are compared at the same ascending edge and at the same descending edge between a symbol edge and another symbol edge, respectively, thereby reducing jitter to the largest extent, improving the yield ratio, and outputting lower sideband digital signals and upper sideband digital signals, the lower sideband digital signals having been delayed by the 1/4 frequency of the carrier frequency; a data demodulation unit for generating a first symbol edge signal detected by aligning the phase difference between a delayed lower sideband positive-phase digital signal and an upper sideband negative-phase digital signal to be 180° and generating a second symbol edge signal detected by aligning the phase difference between a delayed lower sideband negative-phase digital signal and an upper sideband positive-phase digital signal to be 180°, the data demodulation unit overlapping the first symbol edge signal and the second symbol edge signal through an AND gate, thereby reducing the glitch and generating a symbol edge clock, which has no glitch, through a deglitch filter, the data demodulation unit synchronizing the delayed lower sideband positive-phase digital signal with a descending edge of the symbol edge signal, thereby demodulating data; and a data clock restoration unit for generating a data clock using the delayed lower sideband positive-phase digital signal and the demodulated data signal.

    摘要翻译： 本发明的一个实施例涉及一种低功率宽带异步BPSK解调方法及其电路的配置。 结合BPSK解调电路的配置，可以提供一种低功率宽带异步二相移键控解调电路，包括：边带分离和下边带信号延迟单元，用于将调制信号分离成上边带和下边带 使用具有作为其截止频率的载波频率的主高通滤波器和主低通滤波器并将其数字化成正相位和负相位，使得结合来自下边带的数字输出 比较器和来自上边带比较器的数字输出，在符号边缘和另一符号边缘之间的相同上升边缘和相同下降边缘处分别比较具有相反相位的信号，从而最大程度地减小抖动，提高产量 比例，并输出下边带数字信号和上边带数字信号，下边带数字符号 已经延迟了载波频率的1/4频率; 数据解调单元，用于生成通过将延迟的下边带正相数字信号和上边带反相数字信号之间的相位差对齐为180°而检测的第一码元边缘信号，并生成通过对准检测到的第二码元边缘信号 延迟的下边带反相数字信号和上边带正相数字信号之间的相位差为180°，数据解调单元通过与门重叠第一符号边缘信号和第二符号边缘信号，由此减小 所述数据解调单元将所述延迟的下边带正相位数字信号与所述符号边沿信号的下降沿同步，从而对数据进行解调;所述数据解调单元通过去毛刺滤波器生成没有毛刺的符号边沿时钟， 以及数据时钟恢复单元，用于使用延迟的下边带正相数字信号和解调数据信号来产生数据时钟。

    AUDIO FILTERING WITH VIRTUAL SAMPLE RATE INCREASES
    46.
    发明公开
    AUDIO FILTERING WITH VIRTUAL SAMPLE RATE INCREASES 审中-公开
    音频麦芽糖酵母VIRTUELLER ABTASTRATE

    公开(公告)号：EP2979360A4

    公开(公告)日：2017-03-29

    申请号：EP14775520

    申请日：2014-03-26

    申请人： BARRATT LACHLAN PAUL

    发明人： BARRATT LACHLAN PAUL

    IPC分类号： H04R1/22 ,  G01R23/167 ,  G06F3/16 ,  G06F17/17 ,  G06T5/00 ,  G10L21/0332 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H04R3/04

    CPC分类号： H04R3/04 ,  G06F3/165 ,  G06T5/00 ,  G06T2207/20024 ,  G06T2207/20172 ,  G10L21/0332 ,  H03H17/0248 ,  H03H17/0266 ,  H03H17/0286 ,  H03H17/0657 ,  H04R1/22

    摘要： A method of digitally filtering an audio signal using an adjusted audio filter. The adjusted audio filter is represented by an impulse response including a waveform in its time domain represented by a sine function of absolute values. A composite audio filter is derived from two adjusted audio filters although any number of filters may be used. The composite audio filter generally includes a bank of the filters which together define a frequency bandwidth representative of the audio signal or spectrum to be filtered. Also a bandpass filter is constructed by combining frequency responses for sine components of absolute values integrated from 0 to bpf and sine components of absolute values integrated from 1/bpf to 0. The frequency response may be the sum of the frequency responses for each of the filters used to create the composite bandpass filter.

    摘要翻译： 使用经调整的音频滤波器对音频信号进行数字滤波的方法。 经调整的音频滤波器由包括由其绝对值的正弦函数表示的时域中的波形的脉冲响应表示。 复合音频滤波器来自两个调节的音频滤波器，尽管可以使用任何数量的滤波器。 复合音频滤波器通常包括一组滤波器，它们一起定义表示要滤波的音频信号或频谱的频率带宽。 另外，通过将从0到bpf的积分的绝对值的正弦分量的频率响应和从1 / bpf积分的绝对值的正弦分量组合到频率响应构成带通滤波器。频率响应可以是每个频率响应的和 用于创建复合带通滤波器的滤波器。

    SAMPLING RATE CONVERSION DEVICE
    49.
    发明公开
    SAMPLING RATE CONVERSION DEVICE 有权
    采样率转换装置

    公开(公告)号：EP2924879A1

    公开(公告)日：2015-09-30

    申请号：EP13856624.5

    申请日：2013-05-09

    申请人： NTT Electronics Corporation

    发明人： KOIKE, Yuichiro ,  YAMADA, Yasuhiro

    IPC分类号： H03H17/00 ,  H03H17/06

    CPC分类号： H04N19/132 ,  H03H17/0621 ,  H03H17/0642 ,  H04N19/117 ,  H04N19/164 ,  H04N19/167 ,  H04N19/182 ,  H04N19/436

    摘要： A position coordinate difference computing unit (5a to 5c) calculates position coordinate differences between position coordinates of the output digital signals and position coordinates of the input digital signals adjacent to the position coordinates. An FIR coefficient memory (13a to 13c) stores FIR coefficients of an FIR-LPF and outputs FIR coefficients corresponding to position coordinate differences between a fixed number of the output digital signals adjacent to the position coordinates of the output digital signals and the output digital signals. A control unit (11) supplies a group of the FIR coefficients and a group of the input digital signals corresponding to the respective position coordinate differences to the parallel FIR calculator (4) in predetermined order when the position coordinate differences corresponding to two or more different output digital signals are concurrently computed. The parallel FIR calculator (4) performs an FIR-LPF interpolating calculation by using those to obtain the output digital signals.

    摘要翻译： 位置坐标差计算单元（5a至5c）计算输出数字信号的位置坐标与与位置坐标相邻的输入数字信号的位置坐标之间的位置坐标差。 FIR系数存储器（13a至13c）存储FIR-LPF的FIR系数，并输出对应于与输出数字信号的位置坐标相邻的固定数量的输出数字信号与输出数字信号之间的位置坐标差的FIR系数 。 当对应于两个或更多个不同的位置坐标差的位置坐标差异小于预定值时，控制单元（11）将FIR组系数和对应于各个位置坐标差的一组输入数字信号以预定顺序提供给并行FIR计算器（4） 输出数字信号被同时计算。 并行FIR计算器（4）通过使用它们来执行FIR-LPF内插计算以获得输出数字信号。

    SIGNAL GENERATING DEVICE
    50.
    发明公开
    SIGNAL GENERATING DEVICE 审中-公开
    信号发生装置

    公开(公告)号：EP2884660A1

    公开(公告)日：2015-06-17

    申请号：EP13879391.4

    申请日：2013-07-31

    申请人： Mitsubishi Electric Corporation

    发明人： IURA, Hiroki ,  TOMITSUKA, Koji

    IPC分类号： H03H17/00

    CPC分类号： H04L7/0025 ,  H03H17/0227 ,  H03H17/0286 ,  H03H17/0294 ,  H03H17/0621 ,  H03H2017/0222 ,  H04L7/08

    摘要： To provide a signal generating device that can generate an interpolated signal without increasing a memory capacity, at a time of obtaining an interpolated value close to a true value. The signal generating device includes a digital filter unit 1 outputting a first interpolated signal by interpolating an input signal, a digital filter unit 2 outputting a second interpolated signal by interpolating the first interpolated signal, a phase calculation unit 3 calculating a phase of a digital signal, a phase-accuracy conversion unit 4 calculating first phase signal and second phase signal, a memory 5 storing filter coefficients, a coefficient readout unit 6 reading filter coefficients from the memory 5 and switching filter coefficients of the digital filter unit 1, a phase-error calculation unit 7 calculating a phase error signal, a memory 8 storing filter coefficients, a coefficient readout unit 9 reading filter coefficients from the memory 8, and a gain normalization unit 10 normalizing a gain of the filter coefficients to maintain a constant sum of the filter coefficients and switching filter coefficients of the digital filter unit 2.

    摘要翻译： 为了提供一种信号产生装置，该信号产生装置能够在不增加存储器容量的情况下产生内插信号，而在获得接近真值的内插值时。 信号发生装置包括：数字滤波器单元1，其通过内插输入信号来输出第一内插信号;数字滤波器单元2，其通过内插第一内插信号来输出第二内插信号;相位计算单元3，其计算数字信号的相位 ，计算第一相位信号和第二相位信号的相位精度转换单元4，存储滤波器系数的存储器5，从存储器5读取滤波器系数和切换数字滤波器单元1的滤波器系数的系数读出单元6， 计算相位误差信号的误差计算单元7，存储滤波器系数的存储器8，从存储器8读取滤波器系数的系数读出单元9，以及对滤波器系数的增益进行归一化的增益归一化单元10，以保持 数字滤波器单元2的滤波器系数和切换滤波器系数。